Nampally Sai Rukmangad Rohit
Analog Design Engineer | VLSI Specialist | CMOS, Pad Circuits, Cadence Virtuoso | Driving Semiconductor Innovations
Bengaluru
3+ years of work experience
Sep 20242 yrs 1 moPresent
Bengaluru, Karnataka, India
IP Developement - OTD
→ Currently under development of Over temperature Detection module for variations in Temperature to protect the IC from freezing and heating
→ Technology is 12nm FinFet based technology.
IP DEVELOPMENT - POR Circuit
→ Developed a power on reset in 12nm FinFet Technology
→ The circuit is robust for kinds of power profiles.
IP Development – Real Time Clock (RTC)
→ Designed and developed a Real Time Clock operating at 32,768 Hz in 22 nm FDSOI CMOS technology.
→ Developed key sub-blocks including:
→ Beta Multiplier for stable current reference generation.
→ gm-Amplifier for precise sinusoidal signal amplification.
→ Waveform Generators for square wave output.
→ Automatic Loop Control (ALC) for dynamic oscillator stability.
→ Counter Block for accurate timekeeping and frequency division.
→ Optimized the RTC design for low power, high stability, and robust operation across PVT (process-voltage-temperature) variations.
Project – Power-On Reset Circuit
→ Designed a Power-On Reset (POR) circuit in 12 nm LPP FinFET technology (GF12).
→ Ensured reliable system initialization with a fast-response, accurate reset mechanism across PVT variations.
→ Focused on low area and low-power design while meeting stringent FinFET constraints.
Technical Tools & Methodologies
→ Technology nodes: 22 nm FDSOI CMOS, 12 nm FinFET.
→ Design & simulation: Cadence Virtuoso, ADE XL, Spectre.
→ Performed Monte Carlo, Corner, and Transient analyses for performance and reliability verification.
→ Applied best practices in analog IP design, including noise optimization, power efficiency, and signal integrity enhancement.
Jul 202311 mosMay 2024
Bengaluru, Karnataka, India
Analog I/O Design Engineer Intern – Mixed Signal Design Department
→ GPIO Design & Implementation: Designed and implemented 3.3 V GPIO pins operating at pulse frequencies up to 200 MHz.
→ Design Challenges: Addressed fail-safe mechanisms and over-voltage tolerance for 1 MHz pulses, ensuring robust performance under challenging conditions.
→ Output Buffer Development: Developed Level Shifter sub-blocks, Tri-state buffers, Pre-drivers, and Drivers to support pulse specifications of 100 MHz and 200 MHz.
→ Input Buffer Development: Engineered Schmitt Trigger circuits with 300 mV hysteresis sweep, down-conversion blocks, and input buffers for reliable signal reception.
→ Over-Voltage Protection: Designed and implemented protection circuits at the GPIO pad level, safeguarding against voltages above 3.3 V up to a maximum of 5 V.
→ Performance Optimization: Successfully created circuits capable of operating across a broad frequency range (5 MHz to 200 MHz), enhancing overall reliability and robustness.
→ Technical Tools & Methodologies: Utilized 40 nm technology node with Cadence Virtuoso and ADE XL for design and simulation. Performed Monte Carlo and Corner analyses to validate circuit performance under process, voltage, and temperature variations.
Jan 20193 mosMar 2019
Learnt a lot. People over there are good & are full of Knowledge.
Jun 20181 moJun 2018
Greater Hyderabad Area
The Intern was on ESP 32 and STM 32 Under Embedded IOT.
May 20182 mosJun 2018
India
The intern was on Technical study on Inertial Navigation System and GPS in ROCKETS
Nampally’s AI Stack
Education
Master of Technology - MTech, Electronics and Communication Engineering with Specialisation in VLSI
National institute of technology delhi
20222 yrs2024
Bachelor of Technology, Electronics communications and engineering
sreenidhi institute of science and technology
20154 yrs2019
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