Headline

Technical Leader - SI PI | High-Speed Design and Validation

About

Hardware engineer focused on high-speed system design, signal integrity, SERDES, and physical-layer validation. My work sits at the intersection of simulation, lab measurement, board design, silicon interfaces, and IEEE host electrical and optical compliance. I enjoy debugging complex hardware issues where channel behavior, timing, noise, layout, optics, and system-level interactions all matter. I have worked across Cisco, Intel, and Finisar on high-speed platforms, SERDES validation, optical modules, compliance testing, and production hardware.

Location

Bengaluru

AI stack

claude code

codex

Work experience

Technical Lead at Cisco, Sep 2026 - Sep 2026 · 1 mo, Bengaluru, Karnataka, India

Hardware Engineer at Cisco, Oct 2022 - Sep 2026 · 4 yrs, Bengaluru, Karnataka, India, Signal integrity design and validation for high-speed interfaces including Ethernet, PCIE, NRZ, PAM4, DDR Power integrity analysis of PDN systems. SERDES and system bring-up and debug. Host Electrical validation. Optical validation NRZ/PAM4, 1G-100G. Timing Compliance. syncE, PTP.

System Validation Engineer at Intel Corporation, Dec 2021 - Oct 2022 · 11 mos, Penang, Malaysia, Structured ASICs | SERDES | Characterization | Validation | Application

Hardware Engineer at Cisco, Apr 2016 - Dec 2021 · 5 yrs 9 mos, Bangalore, • Developed validation lab in India for high speed electrical, optical and timing compliance. • Worked across multiple Cisco service provider platforms. • Characterized high speed NRZ, PAM4 and coherent interfaces.

Product Engineer at Finisar, Dec 2013 - Sep 2015 · 1 yr 10 mos, Perak, Malaysia, 10G SFP+ Transceiver product engineering

Education

B.Tech, Electronics & Communication Engineering, National Institute of Technology Srinagar