---
title: "Viswateja Mummaneedi - Research Intern in Ananthapuramu | Tal"
description: "Meet Viswateja Mummaneedi, Aspiring RTL Design & Design Verification Engineer | ECE @ IIT (ISM) Dhanbad | Verilog | SystemVerilog | FPGA | Digital Design based in Ananthapuramu. AI stack includes claude code, codex, and deepseek. Explore public work links including github."
image: "https://tal.club/meet/mummaneedi-viswateja/share-image"
---

# Viswateja Mummaneedi on Tal

## Headline

Aspiring RTL Design & Design Verification Engineer \| ECE @ IIT \(ISM\) Dhanbad \| Verilog \| SystemVerilog \| FPGA \| Digital Design

## Location

Ananthapuramu

## AI stack

claude code

codex

deepseek

gemini

github copilot

ChatGPT

## Work experience

Research Intern at Indian Institute of Technology \(Indian School of Mines\), Dhanbad, May 2025 \- Jul 2025 · 3 mos, Dhanbad, Jharkhand, India, Designed and implemented real\-time digital signal processing systems on FPGA hardware as part of a research internship focused on bridging theoretical filter design with hardware realization\. Derived discrete\-time models for Leapfrog and 4th\-order elliptic filters, performed fixed\-point conversion to ensure hardware compatibility, and generated synthesizable Verilog HDL using MATLAB HDL Coder\. Synthesized and validated the complete designs on a Zybo FPGA board using Xilinx Vivado, rigorously comparing FPGA outputs against SPICE and Simulink simulations to verify functional accuracy\. Additionally developed an SPI\-based communication interface with a PMOD AD5541A DAC, programmed ramp and sine waveform generation on the FPGA, and verified analog output signal integrity using an oscilloscope\. Gained hands\-on experience across the full hardware design flow — from algorithm\-level modeling in MATLAB to physical hardware validation — with proficiency in fixed\-point arithmetic, HDL synthesis, timing closure, and analog\-digital interfacing\. Key skills demonstrated: Verilog HDL · MATLAB HDL Coder · Xilinx Vivado · Fixed\-Point Design · SPI Protocol · DAC Interfacing · SPICE/Simulink Co\-simulation · FPGA Synthesis & Validation

Member at E\-Cell, IIT\-ISM, Oct 2024 \- May 2025 · 8 mos, Dhanbad Block, Jharkhand, India

Overall Club Coordinator at Legends In The Making, May 2024 \- May 2025 · 1 yr 1 mo, Dhanbad, Jharkhand, India

Member at Society Of Electronics Engineers, Jan 2024 \- May 2026 · 2 yrs 5 mos, Dhanbad, Jharkhand, India

## Education

Bachelor of Technology \- BTech, Electronics and Communications Engineering, Indian Institute of Technology \(Indian School of Mines\), Dhanbad

## Public links

- github: https://github\.com/viswateja1251

[View the original profile](https://tal.club/meet/mummaneedi-viswateja)

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