Mohit V. profile photo 1 on Tal

Mohit V.

Logic design engineer

Rajasthan

6+ years of work experience

IBM
Jun 20242 yrs 3 mosPresent

Bengaluru, Karnataka, India

Working as part of the P-processor design team under ISDL group. Responsible for the RTL closure of cache coherent fabric design.
Analog Devices
Jan 20231 yr 6 mosJun 2024

Bengaluru, Karnataka, India

Worked in the wireless platforms group on the design of 5G radio. Involved in the RTL design, STA setup, CDC closure, synthesis across two products.
AMD
Jun 20228 mosJan 2023

Hyderabad, Telangana, India

Continuation of my responsibilities at Xilinx.
Xilinx
Jul 20202 yrsJun 2022

Hyderabad, Telangana, India

Worked as part of the interconnect design team under the fabric design group. Worked on the timing characterization, RTL design and post Si debug.
Birla Institute of Technology and Science, Pilani
Jan 20207 mosJul 2020

Pilani

Assisted in lab sessions for 70+ students to teach the applications of Verilog in logic design and computer architecture.

Education

Birla Institute of Technology and Science, Pilani

B.E. (Hons.) Electrical and Electronics Engineering, Electrical and Electronics Engineering

Birla Institute of Technology and Science, Pilani

20164 yrs2020
kendriya vidyalaya

AISSCE

kendriya vidyalaya

20132 yrs2015

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Headline

Logic design engineer

About

RTL Design engineer with a deep interest in computer architecture and signal processing. Posses strong knowledge of implementation tasks like CDC, STA, synthesis, power analysis etc in addition to design.

Location

Rajasthan

Work experience

Logic Design Engineer at IBM, Jun 2024 - Present · 2 yrs 3 mos, Bengaluru, Karnataka, India, Working as part of the P-processor design team under ISDL group. Responsible for the RTL closure of cache coherent fabric design.

Digital Design Engineer at Analog Devices, Jan 2023 - Jun 2024 · 1 yr 6 mos, Bengaluru, Karnataka, India, Worked in the wireless platforms group on the design of 5G radio. Involved in the RTL design, STA setup, CDC closure, synthesis across two products.

Si - Design Engineer 2 at AMD, Jun 2022 - Jan 2023 · 8 mos, Hyderabad, Telangana, India, Continuation of my responsibilities at Xilinx.

Design Engineer 1 at Xilinx, Jul 2020 - Jun 2022 · 2 yrs, Hyderabad, Telangana, India, Worked as part of the interconnect design team under the fabric design group. Worked on the timing characterization, RTL design and post Si debug.

Teaching Assistant at Birla Institute of Technology and Science, Pilani, Jan 2020 - Jul 2020 · 7 mos, Pilani, Assisted in lab sessions for 70+ students to teach the applications of Verilog in logic design and computer architecture.

Education

B.E. (Hons.) Electrical and Electronics Engineering, Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani

AISSCE, kendriya vidyalaya

Mohit V. - Logic Design Engineer in Rajasthan | Tal