Headline

Physical Design Engineer at Radiant Semiconductors

About

Passionate Physical Design Engineer with expertise in ASIC/SoC implementation, specializing in Synthesis-to-GDSII flow, logic aware synthesis, physical aware synthesis, floor planning, power planning, clock tree synthesis, place-and-route, timing closure and sign-off checks. With a strong foundation in VLSI design methodologies. ✔ Chip Implementation – From synthesis to sign-off, ensuring optimal PPA (Power, Performance, Area). ✔ Low-Power Techniques – Experience with Multi-Vt optimization, clock gating, and power gating. ✔ Static Timing Analysis – Familiar with setup, hold, MPW, Xtalk related issues & fixes. The semiconductor industry is at the heart of innovation enabling AI, IoT, and high-performance computing. I am driven by the challenge of pushing the limits of Moore’s Law while balancing power, performance, and area constraints.

Location

Bengaluru

AI stack

deepmind

gemini

metaai

notebooklm

perplexity

ChatGPT

Work experience

Physical Design Engineer at Radiant Semiconductors, Feb 2025 - Present · 1 yr 8 mos

Physical Design Engineer at Radiant Semiconductors, Feb 2025 - Present · 1 yr 8 mos

Physical Design Engineer at RV Skills Design Centre, Aug 2022 - Feb 2023 · 7 mos, Bengaluru

Education

Master of Technology, VLSI Design and Embedded Systems, Ramaiah Institute Of Technology

Bachelor's degree, Electronics and Communications Engineering, P D A College of Engineering, GULBARGA