Headline

Analog Design Engineer - Trainee

About

I’m an Analog Design Engineer Trainee with a strong foundation in electronics, circuit design, and semiconductor fundamentals. I specialize in transistor-level analog circuit design using Cadence Virtuoso, focusing on meeting performance specifications for parameters. My work involves schematic design, simulation, and performance optimization of analog blocks. I’m passionate about VLSI and analog/mixed-signal design, constantly learning about emerging trends in IC design methodologies, low-power techniques.

Location

Kalaburagi

AI stack

claude

gemini

ChatGPT

Work experience

Design Engineer- (Analog design) at SiyaCon Technologies, Jul 2025 - Present · 1 yr 4 mos, On-site, As an Analog Design Engineer Trainee, I am involved in the design, analysis, and verification of analog and mixed-signal circuits for semiconductor applications. My work focuses on understanding transistor-level design principles and optimizing circuit performance. Key Responsibilities: 1) Design and simulate analog circuits such as amplifiers, current mirrors, biasing networks, and voltage references using Cadence Virtuoso. 2) Interpret design specifications to develop efficient transistor-level architectures. 3) Document simulation results and prepare detailed design reports. 4) Collaborate with the layout team for design verification and post-layout analysis.

VLSI Design Engineer intern at Electronics Sector Skills Council Of India (ESSCI), Sep 2024 - Feb 2025 · 6 mos, Kalaburagi, Karnataka, India, designed IEEE 754 32 bit floating point multiplier and performed the formal verification using the UVM also created the GDS II layout using OpenROAD flowscripts and achieved the slack in between (0,1)

Project Intern at Five7 IT Solutions Pvt Ltd, Jul 2024 - Aug 2024 · 2 mos, Kalaburagi, Karnataka, India

Education

Bachelor of Engineering - BE, Electronics and communication engineering, P D A College of Engineering, GULBARGA

PUC, science, Shree guru independent pu college