Headline

RTL Design Engineer | MIPI Subsystems Specialist (CSI2, DSI2, I3C, DPHY, CPHY) | ASIC & FPGA | High Speed | MIPI Multimedia | Design Timing Closure | RDC | CDC | LINTING | SYNTHESIS | RTL SIGNOFF

About

I am an ASIC/RTL Design Engineer specializing in high-performance digital micro architecture and exhaustive formal verification. My expertise bridges the gap between complex structural design and mathematically proven silicon reliability. I have hands-on experience driving Power, Performance, and Area (PPA) optimizations while ensuring RTL robustness through advanced static and formal methodologies. I leverage the Cadence Jasper Gold suite to perform deep structural analysis, automate property extraction, and mathematically eliminate simulation-synthesis mismatches before dynamic verification begins. Technical Expertise: Hardware Description & Assertions: Verilog, SystemVerilog, SVA (SystemVerilog Assertions). Formal Verification: Formal Property Verification (FPV), Sequential Equivalence Checking (SEC), and X-Propagation (XPROP) analysis using Cadence JasperGold. Static Analysis & Sign-off: Advanced structural linting (Jasper Superlint) targeting FSM deadlocks, range overflows, and Reachable X assignments. Clock Domain Crossing (CDC): Comprehensive CDC verification utilizing Jasper CDC for structural mapping, metastability injection, and formal protocol verification.

Location

Bengaluru

AI stack

claude code

claude

deepseek

gemini

Work experience

Engineer I at MAXVY Technologies Pvt Ltd, Aug 2025 - Present · 1 yr 1 mo, Bengaluru, Karnataka, India, Own end-to-end IP development tasks including documentation, micro-architecture creation, implementation, and CDC/RDC/Lint closure. Partner with verification, FPGA, and embedded teams to resolve design issues. Perform extensive debugging in simulation/GLS/FPGA environments and fine-tune IPs for high-performance, real-time operation on FPGA platforms. Performed RTL Linting and Clock Domain Crossing (CDC) / Reset Domain Crossing (RDC) verification using Cadence Jasper, identifying and resolving structural, synchronization, and reset-related design issues. Contributing projects like, ✓CSI2 V4.1 ✓AXI VIDEO STREAM Transceiver ✓AXI LITE ✓DPHY Tx/ Rx etc., Successfully validated MIPI Camera(CSI2) Video IP(DSI2) and DPHY Tx V3.6 systems in FPGA Platforms

Graduate Engineering Trainee at MAXVY Technologies Pvt Ltd, Aug 2024 - Jul 2025 · 1 yr, Bengaluru South, Karnataka, India, As a Graduate Engineering Trainee, I am responsible for contributing to the design and development of digital integrated circuits using Register-Transfer Level (RTL) design methodologies. Creating , implementing, verifying and debugging RTL designs for various digital components, ensuring they meet specified functionality and performance criteria. working / worked on several projects ✓SPD5 HUB(Serial presence detect) ✓SWITCH ✓RCD (Registered clock device - sideband) ✓I3C Master project with DDR driver ✓DSI V2.2 ✓D PHY V3.5 ✓C PHY V 2.1 ✓DPI-2 ✓DBI-2

Internship Trainee at MAXVY Technologies Pvt Ltd, Feb 2024 - Jul 2024 · 6 mos, Tirunelveli, Tamil Nadu, India

Data science and Machine learning Intern at Gilbert Research Center, Oct 2023 - Feb 2024 · 5 mos, Coimbatore, Tamil Nadu, India

Education

Bachelor of Engineering - BE, Electronics and Communications Engineering, V.V.College of Engineering

12th Maths, biology, Hindu higher secondary school Alwarthirunagari