Headline

M.Tech VLSI & Embedded Systems | RTL Design | SystemVerilog | UVM | FPGA | Digital Design Verification | Open to Opportunities

About

Passionate about VLSI design and verification, I specialize in ASIC/FPGA verification, ensuring high-performance, reliable semiconductor solutions. With a strong foundation in Verilog, SystemVerilog, and UVM, I thrive in debugging complex designs and optimizing verification environments. Currently pursuing MTech in VLSI and Embedded Systems, I have a background in Electrical and Electronics Engineering (EEE) and hands-on experience in functional verification, testbench development, and RTL coding. I am eager to contribute to innovative semiconductor projects, leveraging my skills in RTL design, functional verification, and scripting to enhance chip development cycles. Always open to collaboration and learning new methodologies in the ever-evolving VLSI domain.

Location

Chennai

Work experience

RTL Engineer at Jeanuvs, Nov 2025 - May 2026 · 7 mos, Chennai, Tamil Nadu, India

Education

Master of Technology - MTech, Vlsi and Embedded Systems, BSA Crescent Institute of Science and Technology

Bachelor of Engineering - BE, Electrical and Electronics Engineering, Rohini college of engineering and technology