Headline

DESIGN & VERIFICATION (VLSI) DIGITAL DESIGN | VERILOG | SYSTEM VERILOG | UVM (Universal verification methodology) Design and Verification trainee at VLSI GURU

About

Aspiring VLSI Design Verification Engineer with a Bachelor’s of technology in Electronics & Communication Engineering and developed the practical skills in test bench design along with Verification Methodologies through the Digital Fundamentals, Verilog, SystemVerilog, UVM & gained knowledge through academic projects along with internships. Eager to learn best practices and to contribute to the industry.

Location

Tadepalligudem

Work experience

Product Development Intern at Vishnuspire, Contributed to the hardware implementation of the RVM machines throughout the internship, gaining key technical skills and insights.

Design Internship at VlsiGuru, Gained practical experience in design verification through Verilog, System Verilog, UVM and developed the multiple projects during the internship.

Education

Bachelor of Technology - BTech, Electronics and Communications Engineering, Vishnu Institute of Technology (Autonomous)

Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, Vishnu Institute of Technology (Autonomous)