Headline

Physical Design Engineer at Intel

About

Good Experience in Physical Design (RTL to GDS II Implementation/Methodology) Technology Node: 18A/20A/3/7/10/14/16/28/40 nm Areas of Interest: Physical Design, Physical Verification, STA, EM/IR Analysis, Synthesis, LEC, VCLP. Scripting in Perl and Tcl. Tools Used: • Physical Implementation : Fusion Compiler, ICC2, ICC, Innovus, Atoptech’s Aprisa, • Timing analysis : Prime Time, Tempus. • LEC: Conformal. • Physical Verification: Calibre. • Synthesis: Design Compiler, Genus. • ECO: PT-ECO, Tempus-ECO, Dorado/Tweaker MTech in VLSI Design and ES.

Location

Bengaluru

AI stack

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Work experience

Physical Design Engineer at Intel Corporation, Nov 2016 - Present · 9 y 10 mo, Bengaluru, Physical Design

Senior Physical Design Engineer at Qualcomm, Mar 2015 - Sep 2016 · 1 yr 7 mos, Bengaluru Area, India, Physical Design

Staff Engineer, IC Design at Broadcom, Jan 2012 - Mar 2015 · 3 yrs 3 mos, Bengaluru Area, India, Physical Design

Physical Design Intern at Honeywell Technical Solutions Lab, Sep 2010 - Aug 2011 · 1 yr, Bengaluru Area, India, Physical Design

Education

Master of Technology - MTech, VLSI Design and Embedded Systems, Dr.AIT, Bengaluru. VTU

BE, Electronics and Communication Engineering, BTL Institute of Technology, Bengaluru. VTU