Headline

Next Generation FPGA Architecture and Performance Modeling

About

At AMD (Xilinx), my team looks at performance projections for next-gen AMD (Xilinx) ACAP devices. My research group at PES University (https://chips.pes.edu) works on: - building custom accelerators for deep-learning and graph applications - designing PPA-efficient standard cells - simplifying RISCV-based custom design exploration In the past, my students have worked on: - performance modelling of computationally complex algorithms on heterogeneous computing devices such as CPUs, GPUs, and FPGAs. - custom architectures for Deep-learning algorithms - circuit-level exploration for novel FPGAs - accelerators for computationally complex algorithms in Life Sciences and Communications domains using high-level synthesis

Location

Bengaluru

AI stack

claude code

claude

githubcopilot

Work experience

Principal Member of Technical Staff at AMD, Oct 2022 - Present · 4 yrs 1 mo, Hyderabad, Telangana, India

Professor (on Sabbatical) at PES University, Jul 2020 - Present · 6 yrs 4 mos, Bengaluru, Karnataka, India, My research interests lie in design space exploration towards next-generation parallel and customizable computing. At the micro-architecture level, my research looks at coming up with novel computing architecture to address customizable and adaptable parallel computing. I have taught the following courses at the Under-graduate level: - EDA: Verilog-to-Routing - RISCV-on-FPGA

Visiting Professor at AMRITA VISHWA VIDYAPEETHAM, Jul 2020 - Jul 2022 · 2 yrs 1 mo, Bengaluru, Karnataka, India

Associate Professor at AMRITA VISHWA VIDYAPEETHAM, Feb 2015 - Jun 2020 · 5 yrs 5 mos, My research looks at the possibility of a unified compilation framework for heterogeneous computing systems comprising CPUs, GPUs, FPGAs, DSP, etc. At the application level, my objective is to develop parallel computing solutions for computationally complex problems in diverse application domains within high-performance computing, such as life sciences and neuro-morphic computing. I have taught the following courses at the Master's level: - FPGA-based system design - Reconfigurable Computing - GPU architectures and programming in CUDA. Following are some of the research area my PhD scholars are actively working on: - CPU-, GPU-, FPGA-based Heterogeneous Computing, - Circuit-level exploration for novel FPGA architectures - Accelerating computationally complex algorithms in Life Sciences.

Research Associate at Indian Institute of Science, Jul 2013 - Jan 2015 · 1 yr 7 mos, Bengaluru, Karnataka, India, Focus: Simplifying programmability and portability of high-performance computing applications across diverse heterogeneous computing systems.

Postdoctoral Fellow at EPFL, Feb 2010 - Jun 2013 · 3 yrs 5 mos, Lausanne, Vaud, Switzerland, In my post-doctoral research, I have combined the diversity of computation in the two commercially successful architectures, viz., Field Programmable Gate Arrays (FPGAs) and processors. My current research focuses on bridging the performance and usability gap between traditional processors and present-day FPGAs. This research direction has led to the introduction of processor-friendly features in FPGAs by re-thinking the fundamental composition of its reconfigurable fabric. My ideas of re-architecting the FPGA fabric by making VLIW processors viable on FPGAs, have introduced significant performance improvements, especially for Digital Signal Processing applications.

Education

PhD, Electrical Engineering, Paderborn University

M.Sc., Electrical and Computer Engineering, University of Alberta