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Actively Looking for Opportunities | Manual Testing | Post-Silicon Validation (Windows Platform) | Power & Performance | Immediate Joiner

About

Senior Post-Silicon / Platform Validation Engineer with 5.5+ years of experience working on Intel client platforms. Strong hands-on expertise in Windows Platform Validation, Power & Performance testing, and DGPU / Graphics validation across multiple hardware configurations. Experienced in SOC-level validation, benchmark analysis, stress testing, and debugging issues such as BSOD, performance drops, power throttling, and stability failures. Proficient with Intel validation and debug tools including SOC Watch, ITP Toolkit, Fluke DAQ, WPT logs, PySV, DG Diag, and DG Tuner. I have worked closely with cross-functional teams in Agile environments to execute end-to-end validation cycles, improve test coverage, and ensure platform readiness with high quality and on-time delivery. After my last assignment, I focused on upskilling and strengthening my hands-on knowledge in Windows platform validation, Power & Performance debug methodologies, and Python basics for validation automation. I stayed technically active and am fully prepared to contribute immediately. 🔹 Core Skills: • Post-Silicon Validation (Windows Platform) • Power & Performance Validation • DGPU / Graphics Validation • SOC-level Debug & Failure Analysis • BSOD / Hang / Performance Issue Analysis 📍 Location: Bangalore ⏳ Availability: Immediate Joiner I’m actively looking for opportunities in Post-Silicon Validation / Platform Validation / System Validation / SoC Validation roles and am open to full-time or contract positions.

Location

Greater Bengaluru Area

AI stack

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Work experience

Senior Test Engineer at Wipro, Dec 2021 - Nov 2023 · 2 yrs, Bengaluru, Karnataka, India, • Results-driven Validation Engineer with strong experience in Windows platform validation, power & performance testing, and debugging tools. • Skilled in manual testing, test execution, and bug tracking with expertise in high-speed interfaces like HDMI and DP. • Adept at identifying and troubleshooting performance issues, collaborating in Agile teams, and ensuring seamless system functionality. • Executed test cycles, performed regression testing, and validated high-speed interfaces (HDMI, DP). • Worked on Discrete Graphics Programs (GPU) to enhance performance and efficiency. • Conducted Driver-to-Driver (D2D) validation to measure SoC power & performance. • Performed debugging using Pysv, collected logs (Val dump, Scan dump, ETL log, WPT logs, DG tuner). • Created and managed test cases using JIRA, Zephyr, HSD & LIT.

Validation Engineer at UST Global, Jan 2018 - Dec 2021 · 4 yrs, Bengaluru, Karnataka, India, • Execution on D2D (Driver 2 Driver) & OS to OS validation to measure Power & Performance of SOC. • Regression analysis on D2D execution failures by comparing SOC power/performance scores. • Triage on failures by validating in different drivers (passed/engineering/new drivers to find the root cause). • Debugged on blue screen of death (BSOD), system hang issues comparing major part in display driver performance area. • BKM readiness for new platforms E2E PNP executions (BIOS/OS Settings/KPI execution steps etc.) • Supporting Display, 3D, Media, Power Management and VTD (Virtualization for directed) validation on GPU using ATS. • Documenting failures in a bug tracking database and driving for closure with respective owners (BBs/Client) • Work with content team and platform team for trouble shooting of hardware and software issues.

Graphics designer in Epub at Smart icentral technologies, Jul 2015 - Jan 2018 · 2 yrs 7 mos, Mettur Area, India, • Converted hard copies into E-books and E-pub formats using InDesign & OCR. • Developed and debugged HTML & CSS for digital publications. • Analysed program flow to ensure accuracy in output.

Education

Intel

Bachelor’s Degree, Electronics and Communications Engineering, The Kavery Engineering College