Headline

Data Analyst| Business Analyst | SQL, Python, Power BI, Excel | Turning Data into Insights | Engineering Graduate 2025

About

I’m a Data Analyst with an Electronics & Communication Engineering background, focused on turning raw data into clear insights that support better business decisions. I work with SQL, Python, Excel, and Power BI to clean data, analyze trends, track KPIs, and build interactive dashboards for reporting and decision-making. Recently, I built an end-to-end Retail Sales & Profit Analytics Dashboard (2022–2023) where I: cleaned and prepared data using Python wrote SQL queries for KPI and performance analysis created a Power BI dashboard to analyze category, region, shipping mode, and discount vs profit impact I’m actively looking for Data Analyst / Business Analyst roles (India + Gulf region) where I can contribute through strong analytical thinking, structured problem-solving, and data storytelling. Skills: SQL | Python | Power BI | Excel | Data Cleaning | EDA | Data Visualization | KPI Reporting

Location

New Delhi

Work experience

Data Analyst at YouWeRaise, Dec 2025 - Feb 2026 · 3 mos, Noida, Uttar Pradesh, India

Design Verification Engineer- Intern at Futurewiz Pvt Limited, Jan 2025 - Jul 2025 · 7 mos, On-site, • Gained hands-on experience in Advanced Digital Design, Verilog, SystemVerilog, and UVM methodology. • Contributed to RTL design and implementation projects, supporting hardware-optimized solutions. • Developed and simulated digital circuits using tools like ModelSim and Vivado, performing debugging and functional verification. • Applied testbench development techniques and collaborated on protocol-based verification workflows. • Strengthened understanding of SoC architecture, signal integrity, and industry-aligned design practices. Projects: 1. APB Protocol Implementation and Verification Domain: Digital Design & Verification | Language: Verilog | Tools: ModelSim (student), Online Verilog Simulators Methodology: FSM-based Protocol Design, UVM-style Testbench Concepts • Designed and implemented AMBA APB Master and Slave modules using FSM architecture to manage signal handshaking and state transitions. • Developed a SystemVerilog testbench to verify functional correctness of signal activities including PSEL, PENABLE, PREADY, PWRITE, PWDATA. • Integrated basic assertions and functional coverage to validate protocol compliance and improve verification confidence. • Simulated and verified multiple test scenarios successfully, enhancing understanding of SoC bus protocols and modular testbench architecture. • Key Achievement: Demonstrated end-to-end verification of APB protocol aligned with industry-standard DV methodologies. Bluetooth-Controlled Arduino Nano Based Spider Bot Domain: Embedded Systems | Platform: Arduino IDE | Language: Embedded C Tools & Components: Arduino Nano, HC-05 Bluetooth, SG90 Servo Motors, Android App, 3D-Printed Chassis

Design and verification Intern at Futurewiz, Jan 2025 - Jun 2025 · 6 mos, Noida, Uttar Pradesh, India, Gained in-depth knowledge of Advanced Digital Design, Verilog, System Verilog, and Universal Verification Methodology (UVM). •Worked on RTL design and implementation projects, contributing to efficient and optimized hard- ware solutions. •Demonstrated proficiency in coding, simulation, and debugging digital circuits using industry- standard tools.

Education

Certification in Data Analysis(Self Paced), Information Technology, Guardians Edtech and Reva University

Post Graduation- Diploma, ADVLSI, FutureWiz Academy