---
title: "Likith S - VLSI Design Verification Engineer | RTL Verification | SystemVerilog | ASIC DV | Verilog HDL | FIFO Design | UVM (In Progress) in Bengaluru | Tal"
description: "Meet Likith S, VLSI Design Verification Engineer | RTL Verification | SystemVerilog | ASIC DV | Verilog HDL | FIFO Design | UVM (In Progress) based in Bengaluru."
image: "https://tal.club/meet/likith-s/share-image"
---

# Likith S on Tal

## Headline

VLSI Design Verification Engineer \| RTL Verification \| SystemVerilog \| ASIC DV \| Verilog HDL \| FIFO Design \| UVM \(In Progress\)

## Location

Bengaluru

## Education

Bachelor's degree, Electrical, Electronics and Communications Engineering, Central Board of Secondary Education \(CBSE\)

Bachelor's degree, Electrical, Electronics and Communications Engineering, Sri Venkateshwara College of Engineering, BANGALORE

[View the original profile](https://tal.club/meet/likith-s)

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