Headline

AMD Client || Intel || NIT Bhopal

About

As a Physical Design Engineer at SmartSoC Solutions Pvt Ltd, I apply my skills and knowledge in PNR flow, STA, DRC, LVS, timing closure, and ECO implementation to design and optimize SoCs for various clients and applications. I worked with the latest technology nodes, such as TSMC 3nm, 5nm, and 14nm, and handle high-frequency SoCs with up to 2 GHz. I obtained my Master of Technology degree in VLSI Design and Embedded System from Maulana Azad National Institute of Technology in April 2022, where I learned the fundamentals and advanced concepts of circuit design, VHDL, and Synopsys IC Compiler and PrimeTime tools. I also completed a one-year internship at Intel Corporation, where I gained valuable experience in SoC flip chip planning and IO and power bump placement. I am passionate about learning new technologies and techniques in the field of physical design and VLSI, and I am always eager to take on new challenges and opportunities.

Location

Bengaluru

AI stack

claude code

gemini

openai

perplexity

Work experience

Senior Physical Design Engineer at SmartSoC Solutions Pvt Ltd, Jun 2022 - Present · 4 yrs 4 mos, Bengaluru

Physical Design Engineer at AMD, Jun 2022 - Oct 2025 · 3 yrs 5 mos, Banglore

SoC Design Engineer at Intel Corporation, Jul 2021 - May 2022 · 11 mos, Karnataka, India, SoC flip chip planning- Planning of IO and power bumps according to requirements of the SoC & subsystem.

Education

Master of Technology - MTech, VLSI Design and Embedded system, Maulana Azad National Institute of Technology