FPGA design Engineer
Bengaluru, Karnataka, India
Vishakhapatnam, Andhra Pradesh, India
Bachelor of Technology - BTech, Electronics and Communication Engineering
Andhra University College of Engineering
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RTL engineer with good knowledge on digital circuit design, verilog and systemverilog. Proficient knowledge and hands on experience in Handoff flows, spyglass CDC tool,fusion compiler and Caliber flow. Skilled in debugs using synopsis verdi tool. basic knowledge in perl scripting.
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Senior Member Technical at Traana Technologies Private Limited, Sep 2023 - Present · 2 yrs 8 mos, Bengaluru, Karnataka, India
RTL engineer at TechMahindra Cerium systems, Oct 2021 - Sep 2023 · 2 yrs, Vishakhapatnam, Andhra Pradesh, India
Bachelor of Technology - BTech, Electronics and Communication Engineering, Andhra University College of Engineering