Headline

FPGA & Digital Design | Verilog • Xilinx Vivado • AXI | ECE @ NIT Warangal

About

I'm a recent graduate of BTech. ECE from NIT Warangal with deep hands-on experience in FPGA-based digital design, high-speed data pipelines, and embedded systems. Currently at Tonbo Imaging, I architected a Flash-SDRAM bridge pipeline on Xilinx Artix-7. Previously at GalaxEye Space, I built an AXI Scatter-Gather DMA on Zynq UltraScale+. Skills: Verilog HDL | Xilinx Vivado | AXI4 Open to full-time FPGA/Digital Design/VLSI roles. Let's connect!

Location

Warangal Rural

AI stack

antigravity

codex

Work experience

FPGA Intern at Tonbo Imaging, Feb 2026 - Present · 7 mos, Bengaluru

FPGA Intern at GalaxEye, Apr 2025 - Jul 2025 · 4 mos, Bengaluru, Karnataka, India

Intern at Silizium Circuits, Feb 2025 - Feb 2025 · 1 mo, Remote

Executive at Centre for Innovation and Incubation, NITW, Nov 2023 - Jan 2026 · 2 yrs 3 mos, Warangal

Executive at Dance and dramatics club,NITW, Dec 2022 - Dec 2023 · 1 yr 1 mo, Warangal

Education

Bachelor of Technology - BTech, Electronics and Communications Engineering, National Institute of Technology warangal

Grade XII, CBSE, The Indian School, Bahrain