Headline

Senior Chief Engineer @ Samsung Electronics | Text-to-Speech Synthesis, Speech Recognition

About

Speech technology engineer and research lead with extensive experience in text-to-speech, automatic speech recognition, and language modeling. Skilled in neural and statistical speech architectures, text-frontend design, model personalization, and optimization for resource-constrained deployment. Proven record of leading cross-site teams, delivering production-grade speech systems, and advancing research in zero-shot voice adaptation, expressive synthesis. Product Impact: Speech models deployed across Samsung Galaxy devices and voice services used by millions of users globally.

Location

Bengaluru

AI stack

codex

hugging face

mistral

ollama

openai

Work experience

Senior Chief Engineer at Samsung Electronics, Oct 2008 - Present · 18 yrs, Bengaluru, Karnataka, India, [Text-to-Speech] - Researching next-gen TTS architectures for zero-shot voice adaptation, multilingual synthesis, expressive control, and low-latency deployment on handheld devices. - Led end-to-end Gujarati TTS for embedded platforms: talent and corpus design, text-frontend, neural codec/LLM-inspired prior with phoneme-level codec tokens, and MOS/CMOS tuning to production KPIs. - Guided overseas teams on language-specific text-frontends and model maintenance so local engineers can independently sustain and extend TTS systems. - Delivered Turkish and Australian English text-frontends (design, tuning, evaluation) under tight timelines while meeting production KPIs. - Built and deployed handheld-optimized Hindi TTS using a non-attentive Tacotron-style architecture. - Maintain server and on-device British and Indian English TTS, incrementally upgrading architectures as new modeling approaches mature. - Designed a Festival-inspired text-frontend (phrasing, syllabification, stress, POS, G2P/L2S), later simplified as neural models reduced reliance on handcrafted linguistic features. - Developing Transformer-based context-aware G2P for rapid production fixes and scalable multilingual rollout. - Implemented a Multisyn unit-selection engine in C with PSOLA, compressed bitstream relation graphs, and improved Viterbi join-costs via multi-frame averaging. - Built statistical parametric TTS for Indian English, Hindi, and Bengali, with Hindi deployed on mobile; focused on phoneme correctness and prosody via robust linguistic feature pipelines. [Speech Recognition] - Advanced ARPA-based LMs for hybrid ASR (HMM-GMM → HMM-DNN), optimizing HCLG graphs, lexicons, and compact domain-adaptive LMs for contextual accuracy and personalization. - Designed personalization for Transformer ASR using shallow-fusion LMs and dynamic on-the-fly named-entity injection from user IoT data, improving accuracy without retraining acoustics.

Sr. Engineer at AMD, Dec 2005 - Sep 2008 · 2 yrs 10 mos, On-site, - Designed and implemented a golden model for a hardware accelerator on AMD Imageon™ processors, enabling parallel audio signal processing alongside DSP for improved pipeline efficiency. - Developed fixed-point Vorbis decoder reference implementation optimized for Imageon™ handheld processors. - Built OpenMAX (OMX) container component for Ogg format, including metadata parsing, seeking, and related operations. - Implemented and optimized decoders (AC3, EAC3, AAC, aacPlus, MP3) and post-processing algorithms (BBE Process 1 and Process 3) for AMD Xilleon™ Digital TV processors. AAC decoder developed per ARIB Standard B21. All algorithms written in C and assembly, leveraging fixed-point arithmetic.

Sr. MTS at HCL Technologies, Aug 2001 - Dec 2005 · 4 yrs 5 mos, Noida Area, India, - MPEG-4 Video (Part 2): Developed and ported decoder on TI DM270 platform; optimized performance using Imaging Accelerator (MX) and image buffer DMA. - AMR Decoder: Ported and optimized on OMAP1710, adhering to TMS320 DSP Algorithm Interoperability Standard (XDAIS). - ARM–DSP Communication Protocol (OMAP1611): Designed and implemented bidirectional communication and data-sharing mechanisms between ARM and DSP cores. - Audio Codecs: Developed a fixed-point MP3 decoder (ISO/IEC 11172-3, ISO/IEC 13818-3, MPEG-2.5 compliant) and MPEG-2 AAC LC decoder for MIPS TX4972 processor; optimized computational hot spots in assembly. - JPEG Codec: Designed and implemented baseline JPEG encoder and decoder. - VoIP Components: Implemented ITU-T G.711 encoder/decoder, ITU-T Q.23/Q.24 DTMF encoder/decoder, and ITU-T G.168 echo canceller; optimised for ARM7TDMI.

Education

Bachelor of Technology (B.Tech.), Electrical Engineering, Harcourt Butler Technical University (HBTU), Kanpur