---
title: "Kushal Naik K - Embedded Design Engineer in Bengaluru | Tal"
description: "Meet Kushal Naik K, Embedded Design Engineer based in Bengaluru. AI stack includes claude, codex, and cursor."
image: "https://tal.club/meet/kushal-naik-k/share-image"
---

# Kushal Naik K on Tal

## Headline

Embedded Design Engineer

## About

Currently working as an Embedded Design Engineer with a strong foundation in Electrical and Electronics Engineering\. Passionate about embedded systems, power electronics, hardware design, and firmware development\. Experienced in embedded programming, hardware validation, power converter systems, and microcontroller\-based applications\. Skilled in developing and debugging embedded solutions while working with various communication protocols and peripheral interfaces\.

## Location

Bengaluru

## AI stack

claude

codex

cursor

glama

grok

kimi

## Work experience

Embedded Design Engineer at AMEC Technology, Jun 2026 \- Present · 4 mos, Bengaluru, Karnataka, India

Project Associate \- 1 at Central Manufacturing Technology Institute, Nov 2025 \- Jun 2026 · 8 mos, Bengaluru, Karnataka, India, I work on designing and implementing FPGA\-based systems focused on real\-time image processing and machine learning applications\. My role involves developing high\-performance hardware architectures, optimizing algorithms for FPGA acceleration, and writing efficient HDL code for deployment\. I handle module design, verification, and integration using industry\-standard FPGA tools\. I also work on converting ML models into hardware\-friendly formats and implementing them on FPGA for low\-latency inference\. My responsibilities include testing under various conditions, debugging hardware behavior, and improving system accuracy and performance\. Overall, I contribute to building fast, reliable, and scalable FPGA solutions for advanced vision and ML workloads\.

Design Engineer at PRSsemicon Technologies \(A PRSGroup company\), Jun 2024 \- Nov 2025 · 1 yr 6 mos, Chennai, Tamil Nadu, India

Physical Design Engineer at Synapse Design Inc\., Nov 2023 \- May 2024 · 7 mos, Bengaluru, Karnataka, India

ADVANCED VLSI PHYSICAL DESIGN at Maven Silicon, Aug 2023 \- Dec 2024 · 1 yr 5 mos, Bengaluru, Karnataka, India, Executed the full Place and Route \(PnR\) flow, ensuring optimal chip layout for performance, power, and area\. Conducted comprehensive Static Timing Analysis \(STA\) to verify timing closure and identify critical path optimizations\. Utilized advanced tools like PrimeTime for timing signoff and ICC2 and Fusion Compiler for physical design and implementation\. Performed Physical Verification using Calibre to ensure design rule checks \(DRC\) and layout versus schematic \(LVS\) compliance\. Collaborated on end\-to\-end chip design processes, ensuring readiness for tape\-out\. Applied power optimization and area reduction techniques to improve overall design efficiency\.

## Education

Bachelor of Engineering \- BE, Electrical and Electronics Engineering, New Horizon College of Engineering

PUC, PCMC, Narayana Institute

[View the original profile](https://tal.club/meet/kushal-naik-k)

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