Headline

Associate Technical Director | Physical Verification & PEX Methodology | Calibre, ICV, PDK Enablement | CAD & Automation | AI in PV

About

I am a Physical Verification and VLSI CAD professional with 12+ years of experience building scalable methodologies for DRC, LVS, and PEX across advanced technology nodes. Currently working as an Associate Technical Director at Samsung Semiconductor, I lead PV and PEX methodology, driving runset architecture, QA frameworks, and multi-tool correlation across Calibre, ICV, StarRC, xACT, and QRC flows. My core focus areas include: • PV runset architecture and qualification • PEX QA, correlation, and model validation • CAD flow development and automation • Foundry and EDA collaboration for methodology optimization I have led teams, driven end-to-end delivery ownership, and worked as a key escalation point for complex DRC/LVS and extraction challenges. Beyond execution, I am deeply interested in the future of this space — especially applying AI to physical verification, PEX debugging, and design enablement workflows. I enjoy solving hard problems, building scalable systems, and enabling high-quality silicon delivery.

Location

Bengaluru

Work experience

Associate Technical Director – Physical Verification & PEX Methodology at Samsung Semiconductor, Mar 2026 - Present · 6 mos, • Leading Physical Verification and PEX methodology with end-to-end ownership of runset architecture, QA frameworks, and sign-off enablement • Managing and mentoring a team of engineers, driving technical direction, execution, and delivery quality • Driving DRC runset development, qualification, and EDA tool certification across advanced technology nodes • Leading PEX QA and multi-tool correlation across StarRC, xACT, and QRC, improving accuracy and consistency of extraction flows • Acting as the primary escalation point for complex PV debug challenges and custom flow development • Collaborating with foundries and EDA vendors to drive methodology improvements, optimize runtime, and enhance robustness • Driving CAD automation and workflow improvements to reduce turnaround time and improve engineering productivity

Senior Staff Engineer – Physical Verification / PEX at Samsung Semiconductor, Jun 2019 - Feb 2026 · 6 yrs 9 mos, • Led development and qualification of DRC and PEX runsets across advanced nodes • Built and enhanced regression and QA frameworks for scalable PV delivery • Drove multi-tool PEX correlation across StarRC, xACT, and QRC flows • Worked closely with foundries and EDA vendors to resolve complex PV and extraction issues • Contributed to methodology improvements for runtime, accuracy, and robustness

Layout Automation Engineer at Intel Corporation, Feb 2016 - Jun 2019 · 3 yrs 5 mos, Bangalore, CAD Engineer • Developed and maintained ICV-based Physical Verification runsets for IP and SoC design flows • Enabled end-to-end PV environments, including setup, debug, and issue resolution • Improved debug turnaround time by building efficient workflows and automation solutions • Built regression frameworks and validation methodologies to ensure runset quality and consistency • Collaborated with design and methodology teams to translate requirements into robust implementations

Design Engineer at Freescale Semiconductor, Aug 2013 - Jan 2016 · 2 yrs 6 mos, Noida, Uttar Pradesh, India, Custom Design Engineer (June 2015 – Jan 2016) • Designed schematic and layout for test vehicles and DDK blocks • Developed ring oscillator structures for silicon characterization • Created standard-cell layouts adhering to DRC and DFM requirements PDK Engineer (Aug 2013 – May 2015) • Developed Physical Verification runsets (DRC/DFM/Tiling) for PDK releases • Built QA test suites and drove regression closure across multiple designs • Supported cross-team debug and methodology improvements

Intern at STMicroelectronics, Jul 2012 - Jun 2013 · 1 yr, Greater Noida, • Developed DRC/LVS/DFM test suites for PV qualification • Worked on PCell development and ROD-based implementations

Education

Master of Science (M.S.), VLSI CAD, Manipal Academy of Higher Education

Bachelor of Engineering (B.E.), Electronics and Communications Engineering, Global academy of technology