Headline

IP Logic Design Engineer at Intel

About

Seasoned Hardware Design Engineer with 8+ years of experience delivering end-to-end storage and power management subsystems for next-generation SoCs across advanced-nodes (18A, 14A). Proven expertise in low-power architecture, RTL development, UPF implementation, CDC/RDC closure, and timing closure. Passionate about building scalable, power-efficient silicon and solving complex design challenges across the full chip lifecycle from architecture to silicon bring-up.

Location

Bengaluru

AI stack

claude

deepseek

gemini

Work experience

IP Logic Design Engineer at Intel Corporation, Sep 2022 - Present · 4 yrs 1 mo, Banglore

Senior Design Engineer at Marvell Technology, Oct 2021 - Aug 2022 · 11 mos, Hyderabad, Telangana, India

Hardware Design Engineer at rENIAC, Inc, Oct 2018 - Oct 2021 · 3 yrs 1 mo, Greater Hyderabad Area

Hardware Engineering Intern at rENIAC, Inc, Jun 2018 - Sep 2018 · 4 mos, Greater Hyderabad Area

Research Intern at IIIT Hyderabad, May 2017 - May 2018 · 1 yr 1 mo, Greater Hyderabad Area, ● Worked on optimization of Conjugate Gradient algorithm. ● Developed a deeply pipelined and superscalar architecture to enhance the performance of optimized Conjugate Gradient. ● Designed and implemented a Verilog-HDL based parameterizable matrix free conjugate gradient

Education

Bachelor of Technology, Electrical and Electronics Engineering, Mahindra University