Headline

Senior Post-Silicon Validation Engineer | PCIe · CXL · NVMe/Storage | HSIO & System Validation | Python/Pytest Automation

About

I am a Post-Silicon & System Validation Engineer with 7+ years of experience across server platforms, high-speed I/O, storage, automation, and healthcare imaging systems. At Intel, I worked on HSIO, PCIe, CXL, NVMe/Storage, and Xeon server platform validation, covering platform bring-up, test development, automation, execution, debugging, and platform readiness. My experience includes validation of PCIe-attached NVMe storage, VMD, VROC, RAID, Hot-Plug, NPEM, CXL Type-2/Type-3 devices, link states, LTSSM, enumeration, DVSEC/configuration space, resets, recovery, power-management scenarios, and long-duration stress workloads. I have built reusable automation using Python, Shell, and Batch, including automation for large-scale regression execution, result parsing, log collection, failure triage, and hardware cycling. I automated approximately 90% of ~350 storage validation test cases and developed automation for CXL validation workflows. For debugging, I have worked with Teledyne LeCroy PCIe Protocol Analyzer, LTSSM traces, BIOS POST codes, kernel/panic logs, register/configuration-space data, and platform diagnostics. Earlier at GE Healthcare Imaging, I developed Python-based automation and software solutions involving speech-recognition testing, TensorFlow/Keras, computer vision, GStreamer video pipelines, Docker, and system integration. My core areas of interest are Post-Silicon Validation, System/Firmware Validation, PCIe, CXL, HSIO, Storage/NVMe, Server Platforms, Python Automation, and Platform Debug.

Location

Greater Bengaluru Area

AI stack

github copilot

openai

githubcopilot

ChatGPT

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Work experience

System Validation Engineer at Intel, Jun 2021 - Present · 5 yrs 4 mos, Bangalore Urban, Karnataka, India, • Led Post-Silicon System Validation for PCIe/CXL HSIO and Storage across multiple Intel Xeon server platforms, covering validation strategy, platform bring-up, execution, automation, debug, and platform readiness. • Owned validation of PCIe-attached NVMe storage technologies including NVMe, SATA, RAID, VMD, VROC, Hot-Plug, and NPEM across M.2, U.2, U.3, HHHL, and EDSFF form factors. • Developed reusable Python, Shell, and Batch automation frameworks for regression execution, platform configuration, log collection, result parsing, reporting, and automated failure triage. • Automated approximately 90% of ~350 storage validation test cases (~315 tests), enabling scalable regression execution across multiple platform generations and significantly reducing manual validation effort. • Developed automation for CXL Type-2 and Type-3 devices, covering LTSSM/link-state validation, enumeration, DVSEC & PCIe configuration space, speed changes, link recovery, resets, DAX/memory-region workflows, and traffic/stress testing. • Built Quarch Toridon-based NVMe Hot-Plug automation for large-scale plug/unplug, reboot, AC/DC power-cycle, and cycling scenarios with automated device verification, pass/fail detection, and diagnostic log collection. • Debugged complex platform and interconnect failures using Teledyne LeCroy PCIe Protocol Analyzer, LTSSM traces, PCIe configuration/register dumps, BIOS POST codes, kernel/panic logs, and platform diagnostics. • Validated power-management and link-management scenarios, including PCIe ASPM/L1 Substates, platform power states, resets, retraining, recovery, and long-duration stress/stability workloads. • Contributed to Intel Xeon platform validation across Sapphire Rapids (SPR), Emerald Rapids (EMR), Sierra Forest (SRF), Granite Rapids (GNR), and Diamond Rapids (DMR) while improving validation methodology, automation coverage, and internal tooling.

Software Engineer at GE Healthcare, May 2019 - Jun 2021 · 2 yrs 2 mos, Greater Bengaluru Area, • Developed Python-based software, automation, and validation solutions for GE Healthcare medical imaging systems, supporting system integration, testing, and engineering workflows. • Designed and developed a speech-recognition test automation framework for validating voice-driven workflows, improving repeatability and test coverage. • Built a TensorFlow/Keras-based anatomy recognition model, achieving >95% classification accuracy for automated anatomy identification. • Developed and integrated GStreamer-based camera and video-streaming pipelines for imaging and visualization applications. • Developed and evaluated wireless connectivity proof-of-concepts for medical imaging systems, supporting device communication and system integration use cases. • Collaborated with software, systems, validation, and domain engineering teams to debug integration issues, validate functionality, and support healthcare product development.

Intern at GE Healthcare, Aug 2018 - Apr 2019 · 9 mos, Bangalore, • Developed a 3D Time-of-Flight (ToF) based patient-positioning prototype for medical imaging applications using depth/imaging data. • Developed automation solutions for medical imaging/scanner systems, supporting test execution, system interaction, and engineering workflows. • Built a Dockerized GUI/application environment to simplify deployment and execution of internal engineering tools. • Gained hands-on experience with Python, computer vision, imaging systems, Linux, automation, and system integration in a production healthcare engineering environment.

Education

M.Tech Embedded Systems, Embedded systems, Vellore Institute of Technology

Electronics and Communication, Gujarat Technological University (GTU)

Public links

linkedin.com: https://www.linkedin.com/in/kevaljagatiya