---
title: "KAVINDRA PAL - Silicon Engineering Analyst in Bengaluru | Tal"
description: "Meet KAVINDRA PAL, Senior Design Verification Engineer based in Bengaluru. AI stack includes codex, github copilot, and grok."
image: "https://tal.club/meet/kavindra-pal-1/share-image"
---

# KAVINDRA PAL on Tal

## Headline

Senior Design Verification Engineer

## About

VLSI Design Verification Engineer with 4\+ years of experience in SoC and IP\-level verification\. Specialise in UVM/SystemVerilog testbench development, low\-power verification \(UPF\), Gate\-Level Simulation, and protocol verification across PCIe, AXI, and AHB\. Worked across CPU subsystems, cache hierarchies, NAND flash controllers, and PMIC blocks using industry tools including VCS, Verdi, QuestaSim, and Xcelium\. Currently at Accenture, Bengaluru\.

## Location

Bengaluru

## AI stack

codex

github copilot

grok

notebooklm

openai

perplexity

## Work experience

Silicon Engineering Analyst at Accenture, Sep 2026 \- Present · 1 mo, Bengaluru, Karnataka, India

Design Verification Engineer at Excelmax Technologies, Jan 2024 \- Jan 2025 · 1 yr 1 mo, India

Verification Engineer at Cadence Design Systems, Mar 2023 \- Dec 2023 · 10 mos, Bengaluru, Karnataka, India

IP/SOC Verification Engineer at Samsung Semiconductor India, Sep 2022 \- Mar 2023 · 7 mos, Bengaluru, Karnataka, India, low power verification

Design Verification Engineer at Maverick Semiconductor and Services, Aug 2022 \- Sep 2023 · 1 yr 2 mos, Bengaluru, Karnataka, India

[View the original profile](https://tal.club/meet/kavindra-pal-1)

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