Headline

VLSI Physical Verification Engineer

About

Motivated and detail-oriented VLSI Physical Verification (PV) Engineer with hands-on training in ASIC Physical Design and Verification flows. Skilled in running and debugging DRC, LVS, ERC, Density, and Antenna checks using industry-standard EDA tools like Mentor Calibre and Synopsys IC Validator. Strong foundation in CMOS fundamentals, floorplanning, placement, CTS, routing, and TCL scripting. Seeking an entry-level PV / Physical Design opportunity to contribute to zero-defect chip tapeouts and high-reliability silicon layout verification.

Location

Bengaluru

AI stack

claude code

grok

Work experience

VLSI Physical Design & Verification Trainee at Silica Launch, Mar 2026 - Jun 2026 · 4 mos, Bengaluru, - ASIC Physical Verification: Executed DRC, LVS, and ERC cleanups across full-chip and block-level ASIC layouts using Mentor Calibre and Synopsys IC Validator. - Error Analysis & Debugging: Analyzed and resolved layout violations including metal short/open issues, minimum spacing/width rules, antenna rule violations, and density fill requirements. - Physical Design Flow Exposure: Gained end-to-end understanding of ASIC design flow, including Floorplanning, Power Grid Creation, Placement, Clock Tree Synthesis (CTS), and Detailed Routing. - Scripting for Automation: Utilized TCL scripting to automate verification runset execution and streamline error report parsing. - Tapeout Readiness: Practiced layout verification methodologies aligned with foundry sign-off rules and tapeout preparation processes.

Quality Engineer at Schneider Electric, Feb 2025 - Jul 2025 · 6 mos, Bengaluru

Education

Bachelor of Engineering, Electrical and Electronics Engineering, Global academy of technology