Headline

Design Engineer at AMD | EX - INTEL | MTech VLSI Design

About

• Worked with FPGA Prototyping and emulation team • Experienced with FPGA design synthesis and debugging using tools such as VIVADO, synplify •Worked on Haps protocompiler. •RTL Integration of AXI Tracker • Presented project updates and results, effectively communicating technical information in a clear and concise manner. •Experience in verilog and FPGA •Knowledge of protocols :AXI4

Location

Hyderabad

AI stack

claude code

codex

Cline

Work experience

Field-Programmable Gate Arrays Engineer at AMD, Dec 2023 - Present · 3 yrs, Hyderabad, Telangana, India, Power Estimation and Validation using PDM tool Developed and maintained Python-based automation scripts for functional and regression testing Worked on AMD’s latest Versal device support, validating new architecture configurations and features. Contributed to user documentation and user guides of features, creating clear technical content for the use of tools and workflows.

FPGA Prototype and Emulation at Intel Corporation, Sep 2022 - May 2023 · 9 mos, Bengaluru, Karnataka, India

Intern at Intel Corporation, Sep 2022 - May 2023 · 9 mos, Worked on Haps Board, Vivado IDE, and Synplify Executed the FPGA Place and Route (PnR) flow following the partitioning stage using HAPS ProtoCompiler, ensuring efficient implementation and optimization of the design on the target hardware. Integration of AXI4 tracker using system verilog.

Internet of Things training at Ducat Education, Jun 2019 - Aug 2019 · 3 mos, Noida, Uttar Pradesh, India

Education

Master of Technology - MTech, VLSI DESIGN, Vellore Institute of Technology

Master of Science, Electronic Science, Jamia Millia Islamia