Headline

Senior Design Verification Engineer | Ex-Intel Corporation | M.Tech(VLSI Design)

About

Experienced Design Verification Engineer with a demonstrated history of working in the semiconductor industry. Skilled in Universal Verification Methodology (UVM), System Verilog(SV), Verilog, Digital Electronics, Python, Perl and Application-Specific Integrated Circuits (ASIC). Strong engineering professional with a Master of Technology - MTech focused in VLSI Design from VIT University.

Location

Bengaluru

AI stack

claude code

claude

codex

gemini

meta

metaai

Work experience

SoC Design Verification Engineer at Intel Corporation, Jun 2022 - Aug 2026 · 4 yrs 3 mos, Bengaluru, Karnataka, India, Working on VIP integration and bfm instantiation at SoC and sub system levels. Efficiently porting the NIC Env and quickly bringing up NMG env and enabling basic traffic path across multiple IPs

SoC Verification Intern at Intel Corporation, Aug 2021 - May 2022 · 10 mos, Bengaluru, Karnataka, India

Student Partner at Bolt IoT, Nov 2020 - Apr 2021 · 6 mos

Software Engineer Intern at Webeaz Technologies Pvt. Ltd, Mar 2019 - Apr 2019 · 2 mos, Bangalore Urban, Karnataka, India

ASIC Design & Verification Intern at Maven Silicon, Apr 2018 - Mar 2019 · 1 yr, Bengaluru, Karnataka, India

Intern at Bharat Heavy Electricals Limited, Apr 2017 - Jun 2017 · 3 mos, Noida Area, India

Education

Master of Technology - MTech, VLSI DESIGN, Vellore Institute of Technology

Bachelor of Technology - BTech, Electronic and Communications Engineering, Dr. A.P.J. Abdul Kalam Technical University