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Imran Khan

SoC Performance Architect @ Qualcomm | Ex GPU Architect @AMD

Bengaluru

10+ years of work experience

Qualcomm
Apr 20251 yr 5 mosPresent

- Lead Architecture and Peformance analysis for DDR, LLC, NoC for Qualcomm SoC's. - Responsible for SoC/IP Performance modeling, RTL analysis, New Feature exploration and verification. - Identify and fix bottlenecks in DDR, Memory controller, LLC and devise mitigations plans.
AMD
Oct 20231 yr 6 mosMar 2025

Bengaluru, Karnataka, India

• Working on RTL Performance analysis of AMD's AI GPU series of MI3xx Accelerators. • Optimizing the overall architecture and performance by finding the bottlenecks in the GPU architecture for the ML workloads (GPT, LLAMA, GEMMs etc) • Exploration of AMD's next-generation GPU architectures for compute and AI applications.
Qualcomm
Oct 20212 yrsSep 2023

Bengaluru, Karnataka, India

• Lead Architecture and Performance Analysis of Qualcomm's Automotive SoCs at Pre-Silicon Stage and drive the following activities: • Auto SoC Architecture Exploration • Performance Modelling using TLM and SystemC. • Responsible for end-to-end Pre-Silicon Performance Analysis, Conduct Hands-On Studies, Analyze and Identify performance bottlenecks in SoCs for various use cases, Devise mitigation plans for existing performance limitations. • Work with Software and Hardware IP owners to ensure compliance to actual Usecase flow in SoC-based system • Pre-Silicon vs Post-Silicon Usecase correlation activities across core IP owners, Emulation, and Silicon Reference Platforms.
Qualcomm
Oct 20192 yrs 1 moOct 2021

Bengaluru Area, India

• Platform lead for Performance Analysis of Qualcomm's Mobile chipsets using TLM platform, SystemC. • Contribution to the development of Snapdragon 4xx/2xx architecture. • Create and Integrate SoC TLM platform models as per SoC specifications. • Develop and implement new multimedia usecases for performance projections at pre-silicon stage. • Working on Infra components for multiple SoC subsystems (LPDDR5 Memory, ARM SMMU, Display, Camera, Video, Modem, NoCs, and peripherals)
Qualcomm
Jun 20172 yrs 5 mosOct 2019

Bengaluru, Karnataka, India

- Responsible for end to end Pre Si performance analysis for Snapdragon chipsets on TLM platform. - Well versed with SoC architecture definition, exploration and modeling of the multimedia (Camera/Display), Memory subsystems, and Quality of Service (QoS) solutions. - Created new cost-efficient architecture for Snapdragon lower tier chipset, Saved 0.25mm die area on the SoC infrastructure, Validated the performance of new design in the Pre Si TLM platform.
Intel Corporation
Jun 20161 yrMay 2017

Intel Campus, Bangalore, India

At Intel corporation, I implemented the MultiCore methodology on the virtual platform of the next generation Wireless Cellular Modem to speed up the execution of SystemC models of the DSP Cores on TLM platform.
National Institute of Technology Karnataka, Surathkal
Jul 20156 mosDec 2015

NITK

Selected by the Department of Mathematical and computational sciences of NIT Surathkal over more than 100 students for the assistantship. Sponsored by MHRD, Govt. of India.

Imran’s AI Stack

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Education

National Institute of Technology Karnataka

M.Tech, Communication Engineering

National Institute of Technology Karnataka

20152 yrs2017
University of Allahabad

B.Tech, Electronics and Communication Engineering

University of Allahabad

20114 yrs2015

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Headline

SoC Performance Architect @ Qualcomm | Ex GPU Architect @AMD

About

Working on Qualcomm's Snapdragon chipsets architecture design and development, shaping the performance and power of next generation chipsets for Smartphone, PC and IoT products. Received the highest employee recognition award 7 times from Qualcomm in the last 3 years for an excellent contribution to the development of Snapdragon SoC's.

Location

Bengaluru

AI stack

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claudecode

Work experience

Staff Engineer - SoC Performance at Qualcomm, Apr 2025 - Present · 1 yr 5 mos, - Lead Architecture and Peformance analysis for DDR, LLC, NoC for Qualcomm SoC's. - Responsible for SoC/IP Performance modeling, RTL analysis, New Feature exploration and verification. - Identify and fix bottlenecks in DDR, Memory controller, LLC and devise mitigations plans.

MTS, GPU Architecture and Performance at AMD, Oct 2023 - Mar 2025 · 1 yr 6 mos, Bengaluru, Karnataka, India, • Working on RTL Performance analysis of AMD's AI GPU series of MI3xx Accelerators. • Optimizing the overall architecture and performance by finding the bottlenecks in the GPU architecture for the ML workloads (GPT, LLAMA, GEMMs etc) • Exploration of AMD's next-generation GPU architectures for compute and AI applications.

Lead Engineer Sr, Automotive chipset Performance at Qualcomm, Oct 2021 - Sep 2023 · 2 yrs, Bengaluru, Karnataka, India, • Lead Architecture and Performance Analysis of Qualcomm's Automotive SoCs at Pre-Silicon Stage and drive the following activities: • Auto SoC Architecture Exploration • Performance Modelling using TLM and SystemC. • Responsible for end-to-end Pre-Silicon Performance Analysis, Conduct Hands-On Studies, Analyze and Identify performance bottlenecks in SoCs for various use cases, Devise mitigation plans for existing performance limitations. • Work with Software and Hardware IP owners to ensure compliance to actual Usecase flow in SoC-based system • Pre-Silicon vs Post-Silicon Usecase correlation activities across core IP owners, Emulation, and Silicon Reference Platforms.

Senior Engineer - Performance Modeling (Snapdragon 7xx/4xx) at Qualcomm, Oct 2019 - Oct 2021 · 2 yrs 1 mo, Bengaluru Area, India, • Platform lead for Performance Analysis of Qualcomm's Mobile chipsets using TLM platform, SystemC. • Contribution to the development of Snapdragon 4xx/2xx architecture. • Create and Integrate SoC TLM platform models as per SoC specifications. • Develop and implement new multimedia usecases for performance projections at pre-silicon stage. • Working on Infra components for multiple SoC subsystems (LPDDR5 Memory, ARM SMMU, Display, Camera, Video, Modem, NoCs, and peripherals)

Engineer - SoC Performance Modeling at Qualcomm, Jun 2017 - Oct 2019 · 2 yrs 5 mos, Bengaluru, Karnataka, India, - Responsible for end to end Pre Si performance analysis for Snapdragon chipsets on TLM platform. - Well versed with SoC architecture definition, exploration and modeling of the multimedia (Camera/Display), Memory subsystems, and Quality of Service (QoS) solutions. - Created new cost-efficient architecture for Snapdragon lower tier chipset, Saved 0.25mm die area on the SoC infrastructure, Validated the performance of new design in the Pre Si TLM platform.

Intel at Intel Corporation, Jun 2016 - May 2017 · 1 yr, Intel Campus, Bangalore, India, At Intel corporation, I implemented the MultiCore methodology on the virtual platform of the next generation Wireless Cellular Modem to speed up the execution of SystemC models of the DSP Cores on TLM platform.

Graduate Teaching Assistant at National Institute of Technology Karnataka, Surathkal, Jul 2015 - Dec 2015 · 6 mos, NITK, Selected by the Department of Mathematical and computational sciences of NIT Surathkal over more than 100 students for the assistantship. Sponsored by MHRD, Govt. of India.

Education

M.Tech, Communication Engineering, National Institute of Technology Karnataka

B.Tech, Electronics and Communication Engineering, University of Allahabad