---
title: "Hemant Yaduvanshee - Lead Member Of Technical Staff in Noida | Tal"
description: "Meet Hemant Yaduvanshee, Lead Product Validation Engineer | EDA Tool Validation & Automation | Experienced with NVIDIA | Formal Verification & SystemC Expert | Siemens EDA | PG-Diploma in VLSI Design from CDAC based in Noida."
image: "https://tal.club/meet/hemant-10/share-image"
---

# Hemant Yaduvanshee on Tal

## Headline

Lead Product Validation Engineer \| EDA Tool Validation & Automation \| Experienced with NVIDIA \| Formal Verification & SystemC Expert \| Siemens EDA \| PG\-Diploma in VLSI Design from CDAC

## About

I’m a Product Validation Engineer with over 8 years of experience validating semiconductor design and verification tools\. Currently working as a Lead Product Validation Engineer at Siemens EDA, I focus on ensuring EDA tools are accurate, efficient, and reliable in real\-world customer environments, including NVIDIA\. My work connects engineering and customer success \- validating tools that drive next\-generation chip design\. Core Expertise: Test Development & Automation: Designing and executing test plans in C\+\+ and SystemC for formal coverage tools, and automating validation flows for efficiency\. Product Requirement Analysis: Translating specifications and customer workflows into effective validation strategies\. Customer Issue Support: Troubleshooting and resolving customer\-reported issues in collaboration with R&D and application teams\. Product Evaluation & Benchmarking: Assessing tool performance in NVIDIA and customer environments to ensure production readiness\. EDA & Semiconductor Expertise: Skilled in C\+\+/SystemC design, formal coverage \(CCoverCheck\), and equivalence checking \(SLEC / SLEC\-HLS\)\. Validated Tools & Features: Catapult Formal CoverCheck – Formal verification of unreachable coverage targets in HLS CFormal SLEC / SLEC\-HLS – Formal equivalence checking for C\+\+ to RTL flows Catapult Coverage – Coverage correlation between C\+\+ and RTL I work closely with developers, application engineers, and customers to improve tool usability and quality\. I’m passionate about automation, continuous improvement, and delivering production\-grade EDA solutions that set new benchmarks for performance and reliability\.

## Location

Noida

## Work experience

Lead Member Of Technical Staff at Siemens EDA \(Siemens Digital Industries Software\), Jan 2022 \- Present · 4 yrs 6 mos, Noida, Uttar Pradesh, India, Catapult Formal CoverCheck accelerates Catapult HLS source code coverage closure by using formal methods to generate counterexamples for reachable code, and waivers for unreachable code

Senior Member Of Technical Staff at Siemens EDA \(Siemens Digital Industries Software\), Jan 2020 \- Dec 2021 · 2 yrs, Noida, Uttar Pradesh, India

Member Of Technical Staff at Siemens EDA \(Siemens Digital Industries Software\), Feb 2018 \- Dec 2019 · 1 yr 11 mos, Noida Area, India

Post Silicone Validation Engineer at Microsemi Corporation, Nov 2016 \- Feb 2018 · 1 yr 4 mos, Hyderabad Area, India, \-Worked in Lab environment and Familiar with lab equipment like Ethernet Traffic generators, Oscilloscope, logic analyzer\. \-Working knowledge of applications software, Perl and tool command languages \(TCL/TK\) \. used for developing validation testcases, environment\. \-Working knowledge of Linux, Batch scripting, Makefiles and software revision control\. \-Familiarity with HDL’s \- Verilog/VHDL, System Verilog \-Able to work in a challenging and engaging work environment that promotes teamwork, creativity, accountability and professional development \-Post\-Si Validation of Ethernet 10/100/1G/10G switches and Phys\. \-IEEE 1588 \-IEEE 802\.3

## Education

PG, AI Engineering on Cloud and AIOps, Indian Institute of Technology, Roorkee

PG\- Diploma in VLSI System Design, VLSI Design, Centre for Development of Advanced Computing \(C\-DAC\)

[View the original profile](https://tal.club/meet/hemant-10)

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