Harshvardhan
SDE Intern @Tower Research Capital | ex-SWE Intern @ Enterpret, LinkedIn, Texas Instruments | CSE@IIIT-H’26 | Expert @CodeForces
Hyderabad
1+ year of work experience
Jan 20264 mosPresent
Gurugram
Building Strategy Research Framework/Platform for new TRAM/Mid Frequency Teams ... [NDA]
Sep 20255 mosJan 2026
San Francisco Bay Area
As part of ML Team,
I) Enhanced Customer Feedback Intelligence: Improved recall and precision by 25% for a complex 5-level hierarchical aspect classification system by implementing LLM-based refinement layers and high-dimensional NLP processing.
II) Optimized Operational Efficiency: Architected "Insight Sentinel," a front-end filter stage to identify non-actionable feedback, reducing downstream computational overhead and processing costs by 15%.
III) Engineered Scalable Backfill Strategy: Designed an advanced pipeline featuring automated synonym generation, morphological inflection handling, and LLM-based precision filtering; this infrastructure improved recall by 30% when backfilling aspects for evolving keyword taxonomies.
Jun 20254 mosSep 2025
Bengaluru
🔹 Generative AI & Data Processing – Building a GPT-4o powered pipeline to classify noisy job data, replacing legacy systems to significantly improve data quality and recall in production.
🔹 Agentic AI & System Design – Designing and prototyping an agentic AI assistant for LinkedIn Recruiter to automate complex multi-step workflows like candidate search, outreach, and scheduling.
🔹 System Architecture & Tool Integration – Architecting a scalable, server-orchestrated system (MCP) that simplifies development by wrapping internal gRPC services and third-party APIs into standardized tools for AI agents.
🔹 Production Ramping & Evaluation – Performing offline evaluations for coverage and quality, and managing the ramp-up of LLM-based inference into the live production environment using configurable toggles.
May 20252 mosJun 2025
Bengaluru
🔹 Designed and implemented a portable, reusable test suite generation framework for internal IP (e.g., SCI peripheral) to be adapted across multiple projects such as AWR39xxDV, AWR68xx, AWR29xx , etc.
🔹 Developed a Python-based automation tool that reads metadata files (interrupts, processor types, init sequences) and auto-generates processor-specific test configurations (MSS/DSS across Cortex-R, Cortex-M, and DSP cores), increasing test suite reusability by 60%.
🔹 Standardized test methodology to support project- and processor-independent validation, reducing redundant test maintenance overhead by 40%.
🔹 Wrote boot code from scratch for Cortex-R52+ cores on Gen-3 automotive radar SoCs, using R5 boot code as reference.
🔹 Analyzed TRM (Technical Reference Manual) of Cortex-R52+ to identify differences in clocking, MPU, PMU, mutexes, and integrated changes into a custom NoRTOS environment.
🔹 Ported and validated micro-benchmark tests on R52+ to verify bring-up and performance characteristics.
May 20252 mosJun 2025
Hyderabad, Telangana, India
Worked on Model Finetuning for military project Saamvad-ai [NDA restrictions]
Harshvardhan’s AI Stack
Education
B.Tech + M.S., Computer Science Engineering
International Institute of Information Technology Hyderabad (IIITH)
20215 yrs2026
Std. 7 - 12
Chinmaya Vidyalaya, Bokaro Steel City
20156 yrs2021
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