---
title: "Harshitha G - RTL Design and Verification Intern in Greater Bengaluru Area | Tal"
description: "Meet Harshitha G, VLSI Engineer | RTL Design · Verification · Physical Design · RTL-to-GDSII | Verilog · UVM · Cadence · OpenROAD | ECE Graduate – Global Academy of Technology | CGPA 8.08 based in Greater Bengaluru Area."
image: "https://tal.club/meet/harshitha-g-1/share-image"
---

# Harshitha G on Tal

## Headline

VLSI Engineer \| RTL Design · Verification · Physical Design · RTL\-to\-GDSII \| Verilog · UVM · Cadence · OpenROAD \| ECE Graduate – Global Academy of Technology \| CGPA 8\.08

## About

I am an Electronics and Communication Engineering undergraduate at Global Academy of Technology, Bengaluru \(CGPA: 8\.08\), with hands\-on experience in VLSI design, RTL development, and ASIC design flows\. I am proficient in Verilog, C Programming, Python, and TCL scripting, with demonstrated expertise using Cadence and OpenROAD tools\. I have proven ability to execute complete RTL\-to\-GDSII flows with optimized power and area metrics across academic and professional environments\. Currently working as an R&D Intern at VLSI Technology, Semiconductor Division, Bengaluru, where I received a Pre\-Placement Offer \(PPO\) in recognition of strong performance and technical contribution\. Core skills: • RTL Design & Verification — Verilog, SystemVerilog, UVM, AXI Protocol, Ethernet MAC • Physical Design — Floorplanning, Place & Route, CTS, DRC/LVS, RTL\-to\-GDSII • EDA Tools — Cadence Genus/Innovus, Xilinx, OpenROAD, MATLAB • Design Flows — Logic Synthesis, Timing Closure, CDC, Multi\-Corner STA • Scripting — Verilog, TCL, Python, C, Shell • OS — Ubuntu \(Linux\), Windows Open to VLSI opportunities \| Bengaluru \| On\-site & Hybrid

## Location

Greater Bengaluru Area

## Work experience

RTL Design and Verification Intern at VLSIGuru Training Institute, Jan 2026 \- Present · 5 mos, Bengaluru, Karnataka, India, • Completed hands\-on training in Digital Design, Verilog, SystemVerilog, and UVM for ASIC/SoC verification\. • Worked on Verilog design and verification projects including AXI protocol, Ethernet MAC functional verification, and RTL debugging concepts\. • Gained exposure to ASIC Verification Flow, Linux commands for hardware verification and automation\.

VLSI Intern at SkillHigh, Jun 2025 \- Oct 2025 · 5 mos, Hyderabad, Telangana, India, • Completed a 4\-month online industrial internship training program in VLSI design and verification methodologies\. • Gained practical exposure to digital circuit design, Verilog\-based simulations, and advanced verification tools\.

## Education

Bachelor of Engineering \- BE, Electronics and communication, Global academy of technology

[View the original profile](https://tal.club/meet/harshitha-g-1)

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