---
title: "Harsh Kumar - Principal Architect in Santa Clara | Tal"
description: "Meet Harsh Kumar, Principal Architect : Cache Coherent Interconnect based in Santa Clara."
image: "https://tal.club/meet/harsh-111/share-image"
---

# Harsh Kumar on Tal

## Headline

Principal Architect : Cache Coherent Interconnect

## About

CPU Architecture and Micro\-Architecture Verification of custom ARM and x86 Processors\. Cache Coherency verification of custom ARM CPUs with both Industry standard \(AMBA\) and custom specification\.

## Location

Santa Clara

## Work experience

Principal Architect at NVIDIA, Feb 2024 \- Present · 2 yrs 6 mos, Santa Clara, California, United States

Principal Engineer at NVIDIA, Jun 2022 \- Mar 2024 · 1 yr 10 mos, San Francisco Bay Area, Responsible for defining Cache Coherency Protocol for NVIDIA CPU Projects with multi\-core CPUs\.

Sr Design Engineer at NVIDIA, Nov 2019 \- Jun 2022 · 2 yrs 8 mos, Santa Clara, California, United States

Intern R & D at Arm, Jun 2010 \- Jan 2011 · 8 mos, Summer Intern at ARM R&D, Cambridge UK

Design Engineer at AMD, May 2009 \- Sep 2009 · 5 mos, Bengaluru Area, India, SOC verification engineer for the Fusion chip\.

Member of Technical Staff 2 at Montalvo Systems/Sun Microsystems, Jul 2006 \- Jan 2009 · 2 yrs 7 mos, Bengaluru Area, India, CPU \(custom x86\) Architecture Validation\.

Intern at IBM Global Business Services, Feb 2006 \- May 2006 · 4 mos, Bengaluru Area, India, Summer Intern working with IBM Software team\.

## Education

MSc\., Microelectronic Systems, University of Liverpool

B\.E\., Computer Science and Engineering, B\. M\. S\. College of Engineering

[View the original profile](https://tal.club/meet/harsh-111)

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