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Harsh Kumar

Principal Architect : Cache Coherent Interconnect

Santa Clara

10+ years of work experience

NVIDIA
Feb 20242 yrs 6 mosPresent

Santa Clara, California, United States

NVIDIA
Jun 20221 yr 10 mosMar 2024

San Francisco Bay Area

Responsible for defining Cache Coherency Protocol for NVIDIA CPU Projects with multi-core CPUs.
NVIDIA
Nov 20192 yrs 8 mosJun 2022

Santa Clara, California, United States

Arm
Jun 20108 mosJan 2011

Summer Intern at ARM R&D, Cambridge UK
AMD
May 20095 mosSep 2009

Bengaluru Area, India

SOC verification engineer for the Fusion chip.
Jul 20062 yrs 7 mosJan 2009

Bengaluru Area, India

CPU (custom x86) Architecture Validation.
IBM Global Business Services
Feb 20064 mosMay 2006

Bengaluru Area, India

Summer Intern working with IBM Software team.

Education

University of Liverpool

MSc., Microelectronic Systems

University of Liverpool

20091 yr2010
B. M. S. College of Engineering

B.E., Computer Science and Engineering

B. M. S. College of Engineering

20024 yrs2006

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Headline

Principal Architect : Cache Coherent Interconnect

About

CPU Architecture and Micro-Architecture Verification of custom ARM and x86 Processors. Cache Coherency verification of custom ARM CPUs with both Industry standard (AMBA) and custom specification.

Location

Santa Clara

Work experience

Principal Architect at NVIDIA, Feb 2024 - Present · 2 yrs 6 mos, Santa Clara, California, United States

Principal Engineer at NVIDIA, Jun 2022 - Mar 2024 · 1 yr 10 mos, San Francisco Bay Area, Responsible for defining Cache Coherency Protocol for NVIDIA CPU Projects with multi-core CPUs.

Sr Design Engineer at NVIDIA, Nov 2019 - Jun 2022 · 2 yrs 8 mos, Santa Clara, California, United States

Intern R & D at Arm, Jun 2010 - Jan 2011 · 8 mos, Summer Intern at ARM R&D, Cambridge UK

Design Engineer at AMD, May 2009 - Sep 2009 · 5 mos, Bengaluru Area, India, SOC verification engineer for the Fusion chip.

Member of Technical Staff 2 at Montalvo Systems/Sun Microsystems, Jul 2006 - Jan 2009 · 2 yrs 7 mos, Bengaluru Area, India, CPU (custom x86) Architecture Validation.

Intern at IBM Global Business Services, Feb 2006 - May 2006 · 4 mos, Bengaluru Area, India, Summer Intern working with IBM Software team.

Education

MSc., Microelectronic Systems, University of Liverpool

B.E., Computer Science and Engineering, B. M. S. College of Engineering

Harsh Kumar - Principal Architect in Santa Clara | Tal