Headline

VLSI Engineer | DFT | Digital Design | Verilog | Python | Aspiring Chip Design Engineer | CMRIT | Open to Opportunities

About

I am an aspiring VLSI/DFT Engineer with a strong foundation in Digital Electronics, CMOS design, and Design-for-Testability (DFT), currently pursuing my engineering degree at CMR Institute of Technology. I specialize in understanding how chips are designed, tested, and optimized for reliability. My focus areas include scan-based testing, fault modeling (stuck-at, transition faults), and improving fault coverage using efficient test strategies like Launch-on-Capture (LOC) and Launch-on-Shift (LOS). Through hands-on learning and academic projects, I have built a strong base in: • Verilog-based digital design • Scan chain architecture and ATPG concepts • CMOS fundamentals and timing analysis • Python for problem-solving and automation I am particularly interested in solving real-world chip testing challenges — reducing test time, improving coverage, and ensuring silicon reliability. Currently, I am seeking opportunities in VLSI/DFT where I can contribute to high-impact semiconductor projects while continuing to grow as a design and test engineer. Let’s connect if you’re working in VLSI, DFT, or semiconductor design.

Location

India

Work experience

Intern at S2C Semiconductors, Feb 2026 - May 2026 · 4 mos, Bengaluru, Karnataka, India, Completed internship training in DFT with hands-on exposure to Cadence Genus and Modus tools. Learned basics of scan chain architecture, digital electronics, CMOS concepts, Verilog HDL, and Linux commands used in VLSI design flow.

Education

CMR Institute Of Technology

Bachelor of engineering, Electronics and Communication Engineering, CMR Institute Of Technology