Headline

Engineer@Cadence | Ex- Digital Design Intern@Texas Instruments | BITS Pilani

About

Hello! I'm Gunnit Ahuja, 2025 EIE graduate from BITS Pilani. I have a deep passion for Digital & Analog Electronics, and I'm proficient in industry-standard tools such as Cadence Conformal, Cadence Virtuoso, TCAD, and LTSpice. Additionally, I have strong programming skills in Verilog, System Verilog, C++, and C. I’ve also gained hands-on experience in the RTL Design and digital implementation of high-speed data transmission interfaces. I'm committed to leveraging my knowledge and skills to contribute to cutting-edge innovations in the field.

Location

Bengaluru

AI stack

claude code

claude

github copilot

ChatGPT

Work experience

Engineer I at Cadence, Sep 2025 - Present · 1 yr 2 mos, Bengaluru, Karnataka, India

Digital Intern at Texas Instruments, Jan 2025 - Jul 2025 · 7 mos, Bengaluru, Karnataka, India, Designed and verified RTL modules for PHY-level SerDes transmitter and receiver datapaths using Verilog and performed functional simulation in Xilinx Vivado.

Summer Research Intern at Atomic Energy Regulatory Board, May 2023 - Jul 2023 · 3 mos, - Conducted a Dynamic Response Assessment of In-Core Neutron Detectors with a focus on signal analysis - Modeled Vanadium Self-Powered Neutron Detectors using MATLAB and conducted a study to bring out their characteristics and improve dynamic response time of Vanadium Self-Powered Neutron Detectors

Education

Bachelor of Engineering - BE, Electronics and Instrumentation Engineering, Birla Institute of Technology and Science, Pilani - Goa Campus

High School Diploma, PCM, Sanskriti School, New Delhi

Public links

github: https://github.com/Gunnit223