---
title: "Gaurav K. - Senior Design Engineer - DFT in Bengaluru | Tal"
description: "Meet Gaurav K., Sr. DFT Engineer@NXP Semiconductors | IIT Patna’24 (Institute Silver Medal🏅) | CVPR 2024 | Ex Intern@NXP Semiconductors based in Bengaluru. AI stack includes claude code, claude, and codex."
image: "https://tal.club/meet/gaurav-kumar-34/share-image"
---

# Gaurav K\. on Tal

## Headline

Sr\. DFT Engineer@NXP Semiconductors \| IIT Patna’24 \(Institute Silver Medal🏅\) \| CVPR 2024 \| Ex Intern@NXP Semiconductors

## About

I am a Digital Design \(DFT\) Engineer with 2 years of experience at NXP Semiconductors, specializing in UWB and Personal Healthcare SoCs\. I work across the full spectrum Non‑ATPG DFT, with strong hands\-on expertise in RTL\-level DFT implementation, IJTAG architectures, MBIST integration, and DFT\-driven verification\. 🔹 Design for Testability \(DFT\) Expertise \- 2 Years at NXP Core Skills & Responsibilities : Full\-stack experience across ATPG and Non\-ATPG DFT domains UWB SoC DFT implementation involving: > DFT RTL Implementation & Integration > IOs DFT: MFIO, GPIO, I3C pads, TAPC connectivity, TMUX stitching > MBIST: Memory Test & Repair \(MTR\) integration and verification > IJTAG: ICL & PDL development > Non‑ATPG Pattern Generation & Simulation: MBIST, Flash, Boundary Scan, internal IPs, mode transition tests > DFT Security Verification > Power Domain Analysis & Analog\-Digital safe startup strategies Highlights \- Strong in ATPG & Non\-ATPG simulations, MBIST implementation, IJTAG, and MTR wrapper design Proven ability to develop DFT connectivity strategies for complex mixed\-signal SoCs\. 🔹 RTL Synthesis & Physical Design – 1 Year \(Internship\) Radio Frequency Processing SoC Team \(i\) RTL Synthesis > Improved Power, Performance, Area \(PPA\) of RTL blocks > Resolved DFT violations at synthesis stage > Performed LEC, and carried out power estimation \(ii\) Physical Design Worked on advanced\-node flows including: > Floorplanning > Power planning > Placement & routing > Pre‑CTS and Post‑CTS optimization 🔹 EDA Tools Tessent IJTAG, Tessent MBIST, Cadence Genus, Cadence Innovus, Cadence Conformal, Ansys PowerArtist, SimVision, Spyglass 🔹 Innovation & Technical Presentations I actively pursue innovation in DFT methodology and digital design automation\. My recent work has been showcased at major platforms: \(i\) DFT Constraint Generation Strategy – NXP Innovation World Tour, India, 2025 \(ii\) Tessent‑Driven IJTAG Architecture for On‑Chip Frequency Measurement – Siemens User2User Forum, Bangalore, 2026 🔹 Academic Research & Innovation – 1\+ Years in Computer Vision \(IIT Patna\) Worked on cutting\-edge domains such as: > Image Super\-Resolution > Image Denoising & Restoration > Text\-to\-Image Generation \(CLIP\) > Image Contrast Enhancement Our lab’s work was published at CVPR 2024, one of the world’s top computer vision conferences\. Paper: CFAT – Unleashing Triangular Window for Single Image Super\-Resolution

## Location

Bengaluru

## AI stack

claude code

claude

codex

cursor

meta

ChatGPT

## Work experience

Senior Design Engineer \- DFT at NXP Semiconductors, Apr 2026 \- Present · 6 mos, Bengaluru, Karnataka, India, IJTAG, MTR, IOs DFT, Boundary Scan, Non ATPG Verification

Digital Design Engineer \(DFT\) at NXP Semiconductors, Jul 2024 \- Mar 2026 · 1 yr 9 mos, Bengaluru, Karnataka, India, Knowledge of both Scan & Non\-Scan\. Working in Non\-Scan Part of DfT\. Hands\-on experience of JTAG, IJTAG and MBIST pattern generation \+ simulation for different testcases at latest technology nodes\.

Student Intern \- Technical at NXP Semiconductors, Jul 2023 \- Jun 2024 · 1 yr, Noida, Uttar Pradesh, India, I have done Physical/Logical Synthesis using Cadence Genus/ Synopsys Design Compiler, Logic Equivalence Check using Cadence Conformal, RTL/NET power estimation using Ansys\-PowerArtist and Physical Design using Innovus\. I also have experience of writing scripts using python\.

Research in Computer Vision at Indian Institute of Technology, Patna, Jan 2023 \- Jun 2024 · 1 yr 6 mos, Patna, Bihar, India, While pursuing my M\.Tech at IIT Patna, I am working in the field of Image Processing, Pattern Recognition, Computer Vision\. I have worked on both heavyweight & lightweight single image super\-resolution\. While working at IIT Patna our research group got research paper published in IEEE/CVF International Conference on Computer Vision & Pattern Recognition \(CVPR\) 2024\. CVPR amassed an impact score of 63\.10 and an h5\-index of 422 which possesses Rank \#1 among all engineering and computer science publications and Rank \#4 globally among all streams\. Our paper got selected as under the Poster \(Highlight\) category which comprises only top 414 \(11\.9%\) papers out of 2719 accepted papers in CVPR 2024\.

Layout Design Engineer at DXCorr Design Inc, Jan 2022 \- Aug 2022 · 8 mos, Kolkata, West Bengal, India, Worked as VLSI Layout Design Intern\. Made Layout Design of various schematic in Virtuoso Cadence, generated netlist and successfully completed verification ie DRC and LVS\.

Chemistry, Science and Logical reasoning Doubt tutor at Toppr, Feb 2020 \- Feb 2022 · 2 yrs 1 mo, work from home

Subject matter expert at Chegg Inc\., Jan 2020 \- Apr 2023 · 3 yrs 4 mos, work from home

## Education

Master of Technology \- MTech, Dept of Electrical and Electronics Engineering, Indian Institute of Technology, Patna

Bachelor of Technology \- BTech, Electronics and communication engineering, Heritage Institute of Technology

[View the original profile](https://tal.club/meet/gaurav-kumar-34)

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