Headline

Mixed Signal IP Verification Engineer @ Intel Corporation |NITK’26 VLSI Design | TKMCE’22 ECE

About

Verification engineer with an M.Tech in VLSI Design from NITK, Surathkal, and a B.Tech in Electronics and Communication Engineering from TKM College of Engineering. Currently working at Intel as a Mixed-Signal IP Verification Engineer, with hands-on experience in SystemVerilog, UVM, TCL, RTL verification, and regression debugging. Previously, at Intel, I worked on Pre-Silicon Formal Verification using Cadence JasperGold, developing SystemVerilog Assertions (SVA) for protocol and design verification, along with RTL debugging using Synopsys Verdi and regression management using Cadence VManager. Interested in Formal Verification, Design Verification, IP/SoC Verification, and Mixed-Signal Verification, with a strong interest in learning and working on complex hardware verification challenges.

Location

Kollam

AI stack

claude

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openai

perplexity

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Work experience

Mixed signal IP Verification Engineer (Contract) at Intel, Jun 2026 - Present · 4 mos, Bengaluru, Working as a Mixed Signal Verification Engineer on Intel's Hard IP development team, verifying power-integrity Hard IP blocks using SystemVerilog and UVM.

Design Verification Engineering Intern at Intel Corporation, May 2025 - Apr 2026 · 1 yr, Bengaluru East, Worked on formal verification in protocol bridges. Performed formal property verification (FPV) using JasperGold to exhaustively validate design behavior. Developed SystemVerilog Assertions (SVA) to validate protocol correctness, data integrity, and corner-case scenarios.

Education

Master of Technology - MTech, VLSI Design, National Institute of Technology Karnataka

Bachelor of Technology - BTech, Electronics and Communication engineering, TKM College of Engineering , Kollam