---
title: "Divya Teja Reddy Chekkera - Technical Support Engineer in Bengaluru | Tal"
description: "Meet Divya Teja Reddy Chekkera, Technical Support Engineer | UVM · SystemVerilog · AHB-APB · SPI-APB · RAL | Maven Silicon | ASIC & FPGA based in Bengaluru. AI stack includes claude code, claude, and gemini."
image: "https://tal.club/meet/divya-teja-chekkera/share-image"
---

# Divya Teja Reddy Chekkera on Tal

## Headline

Technical Support Engineer \| UVM · SystemVerilog · AHB\-APB · SPI\-APB · RAL \| Maven Silicon \| ASIC & FPGA

## About

VLSI Design Verification Engineer \| Maven Silicon Trained Specialized in UVM\-based testbench development, RTL design, and AMBA protocol verification \(AHB\-APB, AXI4, SPI\)\. Trained under industry mentors at Maven Silicon with hands\-on experience across the full verification lifecycle — from architecture to coverage closure\. What I've built: AHB\-to\-APB Bridge UVM Testbench — 100% functional coverage, 25% reduction in bug detection time\. Engineered modular components: agents, monitors, drivers, and scoreboard using VCS and Questa Sim\. APB\-based SPI Controller Verification — developed UVM testbench with RAL \(Register Abstraction Layer\) model for register\-level verification\. Validated read/write sequences, reset behavior, and boundary conditions across all SPI modes\. 1x3 Packet Router — RTL design with FIFO buffering and arbitration\. 30% latency reduction\. Zero failures across all corner\-case SystemVerilog test scenarios\. 32\-bit Complex Floating\-Point Multiplier — pipelined, power\-efficient design verified on Xilinx and ModelSim with full testbench\-driven validation\. Tools: VCS · Questa Sim · ModelSim · Xilinx Vivado · Synopsys Design Compiler Skills: SystemVerilog · Verilog · UVM · SVA · RAL · RTL Verification · ASIC · FPGA · AMBA Protocols · SPI Published researcher — JETIR \(2024\)\. Immediate joiner\. Open to VLSI/DV roles in Bangalore, Hyderabad, or Chennai\. Open to: → Design Verification Engineer → RTL Design Engineer → ASIC / SoC Verification Engineer → UVM & SystemVerilog Verification Roles → FPGA Design and Verification Preferred locations: Bangalore · Hyderabad · Chennai \| Immediate joiner \| Full\-time

## Location

Bengaluru

## AI stack

claude code

claude

gemini

grok

notion

openai

## Work experience

Technical Support Engineer at Maven Silicon, Nov 2025 \- Present · 11 mos, Bengaluru, Karnataka, India, → Developing UVM\-based verification environments for APB\-based SPI Controller using RAL \(Register Abstraction Layer\) — validating read/write sequences, reset behavior, and boundary conditions across all SPI modes\. → Implementing SystemVerilog Assertions \(SVA\) to validate protocol\-level behavior across APB and SPI interfaces\. → Executing regression test suites and analyzing coverage reports to drive verification closure using VCS and Questa Sim\.

VLSI Trainee at Maven Silicon, Dec 2024 \- Nov 2025 · 1 yr, Bangalore Urban, Karnataka, India, → Built complete UVM testbench architecture for AHB\-to\-APB Bridge verification — achieved 100% functional coverage and reduced bug detection time by 25%\. Components: agents, monitors, drivers, and scoreboard\. → Designed 1x3 packet router in SystemVerilog with FIFO buffering and arbitration logic — reduced packet latency by 30%, passing all corner\-case verification tests\. → Gained hands\-on experience with industry\-standard EDA tools: VCS · Questa Sim · ModelSim · Xilinx Vivado · Synopsys Design Compiler\.

Cyber Security Analyst at Tata Consultancy Services, Apr 2024 \- May 2024 · 2 mos, Hyderabad, Telangana, India, As a Cybersecurity Analyst at TCS, I conducted vulnerability assessments and penetration testing, identifying and mitigating security risks by 30% through proactive monitoring and analysis using Splunk\. Collaborating with a team of four, I helped reduce average incident response times by 20%, ensuring a faster and more efficient security posture for the organization\. My work significantly bolstered the team's ability to handle and resolve security issues swiftly, reinforcing a more robust cybersecurity framework for TCS\.

Python Intern at BRAINOVISION SOLUTIONS INDIA PVT\.LTD, Mar 2023 \- Jun 2023 · 4 mos, Hyderabad, Telangana, India, During my internship at Brain\-O\-Vision, I developed Python\-based automation scripts that enhanced data processing efficiency by 40%, reducing manual data handling time by 50%\. This improvement facilitated smoother workflows, enabling the team to focus more on data insights rather than processing tasks\. My contributions provided the organization with a more efficient way to manage data, significantly improving their operational efficiency\.

## Education

VLSI Design Training Program, Maven Silicon

Bachelor of Technology \- BTech, Electrical and Electronics Engineering, R\.V\.R\. & J\.C\. College of Engineering

[View the original profile](https://tal.club/meet/divya-teja-chekkera)

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