DIVISHA SHARMA profile photo 1 on Tal

DIVISHA SHARMA

Formal Verification | Senior Design Engineer at STMicroelectronics

Delhi

5+ years of work experience

STMicroelectronics
May 20233 yrs 2 mosPresent

Greater Noida

Micron Technology
Jul 20211 yr 10 mosApr 2023

Hyderabad, Telangana, India

Education

Indraprastha Institute of Information Technology, Delhi

M.Tech, VLSI and Embedded Systems

Indraprastha Institute of Information Technology, Delhi

20192 yrs2021
Jamia Millia Islamia

Master of Science, Electronics

Jamia Millia Islamia

20162 yrs2018

Join DIVISHA and 10k+ other professionals on

Tal Boss

Tal is the app where bosses meet engineers & builders directly, without middlemen

Download Tal Boss

DIVISHA SHARMA on Tal

Headline

Formal Verification | Senior Design Engineer at STMicroelectronics

About

I am a passionate and detail-oriented VLSI Design professional with a Master’s degree (M.Tech) in VLSI Design from IIIT Delhi (2019–2021). I have over 4 years of industry experience, currently working as a Senior Design Engineer at STMicroelectronics, where my primary focus is on formal verification. At STMicroelectronics, I specialize in using Cadence JasperGold for performing formal connectivity checks, register verification, and property verification. My work involves writing and debugging SystemVerilog Assertions (SVA) and developing TCL-based automation flows to improve verification efficiency. I have developed strong expertise in Verilog HDL, formal verification methodologies, and digital design principles. Prior to this, I worked at Micron Technology as a Post-Silicon Validation Engineer. My role involved validation and testing of NAND Flash memories, working on UFS (Universal Flash Storage) protocols, and validating critical NAND features. I extensively used Python scripting to automate test flows and data analysis. This experience gave me a strong foundation in memory architecture, post-silicon test methodologies, and system-level debugging. 🔹 Technical Skills • Verification & Design: Formal Verification, SystemVerilog Assertions (SVA), Verilog HDL, Digital Design, STA (Static Timing Analysis) • Tools & Languages: Cadence JasperGold, Python, TCL, UFS Protocol • Other Interests: Static Timing Analysis, Low-Power Design Concepts, RTL Design Methodologies I am driven by a deep interest in digital design and verification, with a strong commitment to learning and contributing to complex VLSI systems.

Location

Delhi

Work experience

Senior Design Engineer at STMicroelectronics, May 2023 - Present · 3 yrs 2 mos, Greater Noida

Engineer MNAND Validation at Micron Technology, Jul 2021 - Apr 2023 · 1 yr 10 mos, Hyderabad, Telangana, India

Education

M.Tech, VLSI and Embedded Systems, Indraprastha Institute of Information Technology, Delhi

Master of Science, Electronics, Jamia Millia Islamia

DIVISHA SHARMA - Senior Design Engineer in Delhi | Tal