---
title: "Dhaval Girishkumar Shah - Principal Design Engineer in Pune District | Tal"
description: "Meet Dhaval Girishkumar Shah, Principal SoC/RTL Design Engineer | Verilog, AXI IP, ASIC, TCP/IP |NPU Data movement | IP Engineer based in Pune District. AI stack includes antigravity, codex, and opencode."
image: "https://tal.club/meet/dhaval-girishkumar-shah/share-image"
---

# Dhaval Girishkumar Shah on Tal

## Headline

Principal SoC/RTL Design Engineer \| Verilog, AXI IP, ASIC, TCP/IP \|NPU Data movement \| IP Engineer

## About

With over 12 years of experience in FPGA, ASIC, and SoC design, I contribute to Cadence Design Systems as a Principal Design Engineer\. My work centers on implementing the AXI4 protocol for the IP group, utilizing my expertise in Verilog RTL design, debugging, and synthesis\. Skilled in developing AXI Master and Slave interfaces, I focus on enabling efficient communication between external systems and creating robust IP solutions\. At Cadence, I support synthesis, linting, and debugging processes, ensuring high\-quality outcomes in system design\. My dedication lies in delivering innovative and reliable designs through collaboration and continuous learning, while leveraging my proficiency in AXI and RTL design to address complex system requirements in the semiconductor domain\.

## Location

Pune District

## AI stack

antigravity

codex

opencode

## Work experience

Principal Design Engineer at Cadence Design Systems, Jun 2022 \- Present · 4 yrs 3 mos, India, Implementing AXI4 Protocol for the IP group for communicating to external systems\. Understanding the IP\. Understanding the AXI protocol, and implementing the requirements in verilog\. Upbringing and debugging\. Synth and Lint support\. AXI Master and AXI Slave side implemented\.

IT Analyst at Tata Consultancy Services, Jul 2014 \- Jun 2022 · 8 yrs, Mumbai Metropolitan Region, List of patent \- https://patents\.justia\.com/inventor/dhaval\-shah/ \(Ctrl \+F \-\-> TATA\) 1 \) FPGA:a\) Implemented a system verilog test bench for a project in TCS, using constrained random testbenched\. b\) Conversion from PCIe \(Endpoint\) protocol to/from AXI/AXIlite protocol\. c\)Created a multi\-FIFO as a part of bigger project \(Implemented in HDL\)\. Tested it with varying read and write rates along with basic functional testing\. d\) Learning about programming the board\. Managing the integration of projects\. e\) Designing \(in RTL \) and testing \(using PCIe\- AXI lite \) of latency block for complex system FPGA tools: Edaplayground, Intel HLS, Xilinx HLS, Xilinx Vivado, Questa sim\. Comfortable with systems engineering 2\) Machine Learning: Interested in machine learning field, have self initiated the learning of the same\. Few toy projects were done\. Machine Learning tools: Java \(Eclipse/Netbeans\), Matlab/Scilab, Python, R OS: Linux and Windows 3\) Networking: Solved the problem of determining the web services dependency from network traces\. Made a tool of it in java from scratch\. In the process found and fixed the bug in tool of 10 years\. Conference Paper and demo paper are written and accepted in COMSNET 2019\. Patent is filed for the same\.

Teaching Assistant at Indian Institute of Technology, Bombay, Jul 2012 \- Jul 2014 · 2 yrs 1 mo, IIT B, Assist Professor in various ways like engaging few lectures, setting question paper, deciding upon marking scheme, checking paper, and most important keep the students satisfied\.

## Education

Master's Degree, Biomedical/Medical Engineering \(Signal Processing using wavelets having application in Biomedical\), Indian Institute of Technology, Bombay

Bachelor of Technology \(BTech\), Electrical, Electronics and Communications Engineering, Walchand college of Engg

[View the original profile](https://tal.club/meet/dhaval-girishkumar-shah)

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