Headline

Physical Design Engineer | RTL-to-GDSII | Static Timing Analysis & Floorplanning | Immediate joiner | B.Tech ECE 2025

About

I don’t just study physical design — I’ve already built and closed blocks end-to-end. I work on ASIC physical design, taking designs from RTL to GDSII while solving real problems like timing violations, congestion, and signoff challenges. During my projects, I’ve handled everything from floorplanning and placement to CTS, routing, and final signoff, working with industry tools like ICC2, PrimeTime, and StarRC. On a 50K+ cell OpenSPARC T1 block, I improved setup WNS from -2.17ns to near closure and reduced hold TNS from -1187ns to almost zero through buffering, optimization, and ECO iterations. I’ve also dealt with high congestion scenarios (93% routing) and taken designs through DRC, LVS, and RC signoff readiness. My core strength is timing closure — understanding why a design fails and fixing it using the right combination of placement, buffering, sizing, and constraints. I’m comfortable working across 14nm and 28nm nodes and handling multi-clock domain designs with a focus on PPA. I’m now looking for an opportunity as a Physical Design Engineer where I can contribute to real chip tapeouts and grow in a high-performance team. If you’re hiring for physical design roles or know someone who is, feel free to reach out — maddudhanushsai@gmail.com

Location

Bengaluru

Work experience

Trainee at ChipEdge, Jun 2025 - Nov 2025 · 6 mos, Bengaluru, Karnataka, India, Training program in VLSI Physical Design at ChipEdge Technologies

Education

B-TECH (ECE), Raghu Institute of Technology - India

High School Diploma, S.F.S.SchoolVIZAG