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Dhananjay Singh

SOC Design Engineer at ARM | Ex - Intel |M.Tech Microelectronics & VLSI Design |NIT Calicut

Bengaluru

6+ years of work experience

Arm
Jan 20251 yr 9 mosPresent

Hybrid

Intel Corporation
Jul 20222 yrs 7 mosJan 2025

-Design and Integration of DDR Subsystem, ensuring compliance with timing and area constraints. -Owned SoC partitions for CDC/RDC ,managing metastability and ensuring data integrity across clock domains. -Applied UPF methodologies to the DDR Subsystem, ensuring power intent consistency and effective power management. -Collaborated with cross-functional teams to integrate IPs into SoC designs,resolving issues and improving design efficiency. -Conducted VC lint checks on RTL designs, identifying and resolving code quality issues and improving design robustness. -Automated processes using scripting languages improving overall productivity.
Intel Corporation
Jul 20211 yrJun 2022

-Integrated various IP blocks into the System on Chip (SoC) Design,ensuring seamless functionality and performance. -Ramped up and conducted thorough CDC/RDC analysis and implemented solutions to mitigate metastability issues, enhancing the reliability of the SoC. -Utilized industry-standard tools and methodologies to achieve project milestones within deadlines.
Tata Consultancy Services
Nov 20181 yr 2 mosDec 2019

Dhananjay’s AI Stack

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Education

National institute of technology Calicut

M.Tech, Microelectronics & VLSI Design

National institute of technology Calicut

20202 yrs2022
Madan Mohan Malaviya University of Technology

B.Tech, Electronics and Communication Engineering

Madan Mohan Malaviya University of Technology

20144 yrs2018

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Headline

SOC Design Engineer at ARM | Ex - Intel |M.Tech Microelectronics & VLSI Design |NIT Calicut

About

Dedicated SoC Logic Design Engineer with 3+years of experience in Design of DDR/Memory Subsystem, Clock Domain Crossing (CDC), Reset Domain Crossing(RDC) and IP integration in SoC. Proven track record of contributing to high-performance designs at Intel with strong problem-solving skills and attention to detail. Adept at collaborating across teams to deliver efficient, scalable solutions within stringent timelines.

Location

Bengaluru

AI stack

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codex

gemini

Work experience

SoC Design Engineer at Arm, Jan 2025 - Present · 1 yr 9 mos, Hybrid

SoC Design Engineer at Intel Corporation, Jul 2022 - Jan 2025 · 2 yrs 7 mos, -Design and Integration of DDR Subsystem, ensuring compliance with timing and area constraints. -Owned SoC partitions for CDC/RDC ,managing metastability and ensuring data integrity across clock domains. -Applied UPF methodologies to the DDR Subsystem, ensuring power intent consistency and effective power management. -Collaborated with cross-functional teams to integrate IPs into SoC designs,resolving issues and improving design efficiency. -Conducted VC lint checks on RTL designs, identifying and resolving code quality issues and improving design robustness. -Automated processes using scripting languages improving overall productivity.

SoC Design Engineer at Intel Corporation, Jul 2021 - Jun 2022 · 1 yr, -Integrated various IP blocks into the System on Chip (SoC) Design,ensuring seamless functionality and performance. -Ramped up and conducted thorough CDC/RDC analysis and implemented solutions to mitigate metastability issues, enhancing the reliability of the SoC. -Utilized industry-standard tools and methodologies to achieve project milestones within deadlines.

Assistant System Engineer at Tata Consultancy Services, Nov 2018 - Dec 2019 · 1 yr 2 mos

Education

M.Tech, Microelectronics & VLSI Design, National institute of technology Calicut

B.Tech, Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology

Dhananjay Singh - SoC Design Engineer in Bengaluru | Tal