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Deepanshu Gupta

Senior Design Verification Engineer at HCLTech

Bengaluru

4+ years of work experience

HCLTech
Aug 20262 mosPresent

Bengaluru, Karnataka, India

Semi Design
Sep 20251 yrAug 2026

On-site

Working on GDDR6 controller-side subsystem verification, focusing on validating protocol compliance and functional correctness as per JESD250C specifications. Verified key protocol and functional scenarios including initialization, training, refresh, mode register, and read/write operations across functional and corner-case scenarios. Developed SVA checks, directed tests, and constrained-random scenarios to improve protocol validation and bug detection. Built and tracked functional coverage models, achieving 99% coverage and driving closure on uncovered scenarios. Performed regression analysis and debugged RTL/testbench issues for VIP deliverables.
Cadence
Nov 20222 yrs 2 mosDec 2024

Noida, Uttar Pradesh, India

Incise Infotech Private Limited
Jun 20223 yrsMay 2025

India

Incise Infotech
May 20223 yrs 1 moMay 2025

Developed robust UVM-based verification environments for APB,AHB and AXI. Achieved coverage closure through functional and code coverage models (100%). Authored assertions for sequences, clocks, and protocol checks. Executed GLS with zero-delay and SDF back-annotation; debugged setup/hold, race conditions, and X-propagation issues.

Deepanshu’s AI Stack

gemini
gemini

Education

J.C. Bose University of Science and Technology, YMCA

Bachelor of Technology, Electrical, Electronics and Communications Engineering

J.C. Bose University of Science and Technology, YMCA

PCM

Modern Delhi Public School

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Headline

Senior Design Verification Engineer at HCLTech

About

Semi Design benefits from a dedicated ASIC Verification Engineer contributing to DDR-focused projects since May 2025, with expertise in GLS, code coverage, and assertions. Previously, worked at Incise Infotech and Cadence, supporting verification and VIP R&D initiatives. Holds a BTech in Electrical, Electronics, and Communications Engineering from J.C. Bose University. Certified in SystemVerilog and UVM, bringing a strong foundation in advanced verification methodologies to enable efficient design processes. Excels in collaborative environments to deliver high-quality solutions.

Location

Bengaluru

AI stack

gemini

Work experience

Senior Design Verification Engineer at HCLTech, Aug 2026 - Present · 2 mos, Bengaluru, Karnataka, India

ASIC Design Verification Engineer at Semi Design, Sep 2025 - Aug 2026 · 1 yr, On-site, Working on GDDR6 controller-side subsystem verification, focusing on validating protocol compliance and functional correctness as per JESD250C specifications. Verified key protocol and functional scenarios including initialization, training, refresh, mode register, and read/write operations across functional and corner-case scenarios. Developed SVA checks, directed tests, and constrained-random scenarios to improve protocol validation and bug detection. Built and tracked functional coverage models, achieving 99% coverage and driving closure on uncovered scenarios. Performed regression analysis and debugged RTL/testbench issues for VIP deliverables.

VIP R&D Engineer at Cadence, Nov 2022 - Dec 2024 · 2 yrs 2 mos, Noida, Uttar Pradesh, India

Verification Engineer at Incise Infotech Private Limited, Jun 2022 - May 2025 · 3 yrs, India

Verification Engineer at Incise Infotech, May 2022 - May 2025 · 3 yrs 1 mo, Developed robust UVM-based verification environments for APB,AHB and AXI. Achieved coverage closure through functional and code coverage models (100%). Authored assertions for sequences, clocks, and protocol checks. Executed GLS with zero-delay and SDF back-annotation; debugged setup/hold, race conditions, and X-propagation issues.

Education

Bachelor of Technology, Electrical, Electronics and Communications Engineering, J.C. Bose University of Science and Technology, YMCA

PCM, Modern Delhi Public School

Deepanshu Gupta - Senior Design Verification Engineer in Bengaluru | Tal