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Bachelor of Engineering, Electronics and communication
RNS Institute of Technology - India
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Final‑year ECE student specializing in RTL design, FPGA implementation, and protocol verification. Experienced in Verilog/SystemVerilog, AXI4‑Lite, UART, and FPGA tools (Vivado, XSim) with multiple projects achieving timing closure on Xilinx Artix‑7. Passionate about digital design, RISC‑V architecture, and SoC integration, actively seeking RTL/Digital Design internships.
Bengaluru
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Bachelor of Engineering, Electronics and communication, RNS Institute of Technology - India