---
title: "DEEPAK BHARANI - STAFF IC LAYOUT DESIGN ENGINEER. in Bengaluru | Tal"
description: "Meet DEEPAK BHARANI, Full chip RF/ANALOG/PMIC layout designer. based in Bengaluru. AI stack includes claude code, codex, and gemini."
image: "https://tal.club/meet/deepak-bharani/share-image"
---

# DEEPAK BHARANI on Tal

## Headline

Full chip RF/ANALOG/PMIC layout designer\.

## About

Full Chip RF/Analog/PMIC Layout Engineer with a more than a decade of experience and focused on parasitics, matching, and noise\-aware design\. Currently expanding into SoC architecture—building understanding in signal chains, ip integration and power systems—aiming to bridge physical design with system\-level decisions\. \-\-\-> System\-aware semiconductor engineer\.

## Location

Bengaluru

## AI stack

claude code

codex

gemini

github copilot

notebooklm

openai

## Work experience

STAFF IC LAYOUT DESIGN ENGINEER\. at Synaptics Incorporated, May 2025 \- Present · 1 yr 5 mos, Bengaluru, Karnataka, India, Integration engineer\.

IC MASK DESIGNER ADVISORY at INDIAN SYSTEM DEVELOPMENT LAB \(IBM\), Aug 2023 \- Apr 2025 · 1 yr 9 mos, Bengaluru, Karnataka, India, cryocmos layout design

Layout Engineer , LEAD at Qualcomm, Oct 2022 \- Aug 2023 · 11 mos, India, Ip layout design\(rf and mixed signals\)

Senior Layout Engineer at Qualcomm, Apr 2019 \- Nov 2022 · 3 yrs 8 mos, Greater Bengaluru Area

Staff Engineer at Eximius Design, Apr 2017 \- Apr 2019 · 2 yrs 1 mo, BANGALORE , INDIA

Layout Designer at ARF Design Pvt Ltd, Nov 2014 \- Mar 2017 · 2 yrs 5 mos, Greater Bengaluru Area, worked on analog and digital cells, floor plan\. physicial verification\.

## Education

Master's Degree, VLSI and embedded system\., RNSIT

KVGCE, Sullia

[View the original profile](https://tal.club/meet/deepak-bharani)

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