---
title: "Debashis Samanta - Analog Layout Design Engineer in Greater Bengaluru Area | Tal"
description: "Meet Debashis Samanta, SoC Design Engineer at Intel based in Greater Bengaluru Area. AI stack includes gemini and github copilot."
image: "https://tal.club/meet/debashis-s-1/share-image"
---

# Debashis Samanta on Tal

## Headline

SoC Design Engineer at Intel

## About

Analog Layout Engineer \| 4\+ YOE \| TSMC/ Intel Nodes \| Virtuoso \| Calibre DRC/LVS \| LDO, Bandgap, GPIO \| Custom Analog Layout

## Location

Greater Bengaluru Area

## AI stack

gemini

github copilot

## Work experience

Analog Layout Design Engineer at Intel Corporation, Dec 2021 \- Present · 4 yrs 10 mos, On\-site

Teaching Assistant at IIT Bhubaneswar, Jul 2019 \- May 2021 · 1 yr 11 mos

Engineering Trainee at Bharat Sanchar Nigam Limited, Aug 2014 \- Aug 2015 · 1 yr 1 mo

## Education

Master of Technology \- MTech, Electrical, Electronics and Communications Engineering, Indian Institute of Technology, Bhubaneswar

Bachelor of Technology \- BTech, Electrical, Electronics and Communications Engineering, International Institute of Information Technology, Bhubaneswar

[View the original profile](https://tal.club/meet/debashis-s-1)

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