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Debashis Samanta

SoC Design Engineer at Intel

Greater Bengaluru Area

7+ years of work experience

Intel Corporation
Dec 20214 yrs 10 mosPresent

On-site

IIT Bhubaneswar
Jul 20191 yr 11 mosMay 2021

Bharat Sanchar Nigam Limited
Aug 20141 yr 1 moAug 2015

Debashis’s AI Stack

gemini
gemini
github copilot
github copilot

Education

Indian Institute of Technology, Bhubaneswar

Master of Technology - MTech, Electrical, Electronics and Communications Engineering

Indian Institute of Technology, Bhubaneswar

International Institute of Information Technology, Bhubaneswar

Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

International Institute of Information Technology, Bhubaneswar

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Headline

SoC Design Engineer at Intel

About

Analog Layout Engineer | 4+ YOE | TSMC/ Intel Nodes | Virtuoso | Calibre DRC/LVS | LDO, Bandgap, GPIO | Custom Analog Layout

Location

Greater Bengaluru Area

AI stack

gemini

github copilot

Work experience

Analog Layout Design Engineer at Intel Corporation, Dec 2021 - Present · 4 yrs 10 mos, On-site

Teaching Assistant at IIT Bhubaneswar, Jul 2019 - May 2021 · 1 yr 11 mos

Engineering Trainee at Bharat Sanchar Nigam Limited, Aug 2014 - Aug 2015 · 1 yr 1 mo

Education

Master of Technology - MTech, Electrical, Electronics and Communications Engineering, Indian Institute of Technology, Bhubaneswar

Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, International Institute of Information Technology, Bhubaneswar

Debashis Samanta - Analog Layout Design Engineer in Greater Bengaluru Area | Tal