Headline

Computer Architecture | Performance Analysis and Modeling | Systems Performance | C++ • Python | CPU • SoC • AI Accelerators

About

I am a computer architecture and systems-performance engineer with 10+ years across engineering and research, including 5+ years focused on processor and systems performance. My recent work spans Qualcomm Hexagon DSPs, AMD Ryzen CPUs and IBM Power processors, with experience in performance modelling, workload characterisation, microarchitecture analysis, simulator-to-RTL correlation, cache and memory behaviour, benchmarking and bottleneck attribution. I work primarily with C++, Python, simulation, profiling and analytical automation to build performance models, investigate regressions, validate architectural assumptions and understand complex hardware-software interactions. More recently, I have also been applying LLM and agentic workflows to engineering analysis, automation and performance-debugging problems. I am particularly interested in CPU, GPU, SoC and AI-accelerator performance, computer architecture, hardware-software co-design and high-performance systems. I am relocating from Bengaluru to Pune and am exploring senior individual-contributor opportunities in Pune or remote-mode roles.

Location

Pune District

AI stack

antigravity

claude

codex

gemini

hermes agent

openclaw

Work experience

Hardware Developer at IBM, Oct 2024 - Present · 2 yrs, Bengaluru, Karnataka, India, Performance Modeling | IBM Power Core, Multicore & Fabric Develop and analyse C++ performance models for IBM Power processors, spanning core, multicore, cache-coherence and fabric behaviour. Developed a modular Snoop Filter simulation component and integrated it into the performance-modeling infrastructure. Investigated simulator-to-RTL execution and performance correlation using PMU statistics, traces and microarchitectural analysis. Built trace-generation, statistics-capture and multithreaded simulation workflows to support performance analysis and model validation. Developed C++/Python and LLM-assisted tooling for comparing simulation executions, identifying divergences and accelerating microarchitectural debugging. Won the IBM India Systems Development Lab Bob-a-thon 2026 with a solo agentic-coding prototype, competing against 100+ multi-member teams.

Senior Silicon Design Engineer at AMD, Dec 2023 - Jun 2024 · 7 mos, Bengaluru, Karnataka, India, Ryzen CPU Core Performance Modeling Worked with the Ryzen CPU core performance-modeling team on C++ model infrastructure, microarchitecture studies and performance analysis. Performed model-to-RTL correlation and investigated non-correlating performance-monitoring counters (PMCs). Supported regression analysis, PMC post-processing and automation used to evaluate microarchitectural behaviour and model accuracy.

Hardware Engineer at Qualcomm, Nov 2021 - Dec 2023 · 2 yrs 2 mos, Bengaluru, Karnataka, India, Hexagon DSP Pre-Silicon Performance Verification Independently handled pre-silicon performance verification across 3+ Hexagon DSP cores using workload characterisation, performance analysis and statistical methods. Developed directed tests for cache and microarchitectural features and validated behaviour against architectural specifications. Analysed performance counters, workload behaviour and key performance indicators to identify bottlenecks and performance anomalies. Built Python-based analytical and visualisation workflows to accelerate performance investigation and reporting.

Graduate Research Fellow at Department of CSE, IIT Hyderabad, Dec 2017 - Jun 2021 · 3 yrs 7 mos, Hyderabad, Telangana, India, Computer Architecture | DNN Workloads | Hardware Performance Counters Researched the interaction between DNN workloads and processor microarchitecture using hardware performance monitoring counters (PMCs). Characterised cache, branch and instruction-level behaviour of neural-network workloads using statistical and machine-learning techniques. Developed a PMC-based side-channel methodology for inferring DNN layer characteristics, achieving >90% inference accuracy in the research setting. Published the work at ACM AIMLSystems 2021 and released supporting PMC traces for research use.

Senior Technical Assistant 'B' at Defence Research and Development Organisation (DRDO), Jul 2016 - Jan 2018 · 1 yr 7 mos, Hyderabad Area, India, Supported HPC-based experimental and computational workloads and administered research computing infrastructure. Deployed and managed an OpenStack-based private-cloud environment. Explored early quantum-computing workflows using IBM Quantum, including experiments on a 2-qubit system. Subsequently moved into graduate research in Computer Architecture and Systems at IIT Hyderabad.

Education

Master of Science - MS, Computer Science and Engineering, Indian institute of technology Hyderabad

B.Tech, Electronics and Communication Engineering, NIST University

Public links

youtube.com: https://youtube.com/@bhargavachary

bhargavachary.in: https://bhargavachary.in/