Headline

Final year Electronics and Communication Engineering student at Amrita Vishwa Vidyapeetham

About

I am a 4th-year Electronics and Communication Engineering (ECE) student with a strong interest in core electronics and semiconductor-related fields. I enjoy working close to hardware and understanding how systems actually work at a low level. My main areas of interest include VLSI design, Verilog, and FPGA-based systems. I have hands-on experience with tools such as Vivado and LTspice, and I am familiar with Cadence Virtuoso, which I am actively exploring to deepen my understanding of analog and digital design flows. Currently, I am strengthening my skills in Verilog HDL and digital design concepts through practice and projects. Along with this, I am comfortable using tools like Cisco Packet Tracer, MATLAB, Proteus, and Keil, which has helped me build a strong foundation across networking, simulation, embedded systems, and analysis. I actively participate in technical hackathons conducted at my college and enjoy working under time constraints to solve real problems. I recently participated in Smart India Hackathon (SIH) 2025, cleared the internal hackathon round, and have consistently been a finalist in multiple college-level hackathons. These experiences have helped me develop problem-solving skills, teamwork, and the ability to quickly learn and adapt. As a person, I am curious, detail-oriented, and a good listener. I enjoy explaining technical concepts in a simple and clear way, which helps both my own understanding and team collaboration. I like learning by building, experimenting, and improving through feedback. I am looking forward to opportunities that allow me to grow in VLSI, digital design, FPGA development, and hardware design, and to gain meaningful real-world industry exposure while continuing to learn and improve.

Location

Bengaluru

AI stack

claude code

notebooklm

perplexity

ChatGPT

Work experience

Intern at NIELIT, Jun 2026 - Jul 2026 · 2 mos, Remote, Gained hands-on experience with the RTL-to-GDSII flow using Verilator, Yosys, GTKWave, OpenLane, and OpenROAD, covering RTL simulation, synthesis, waveform analysis, physical design, and SoC signoff.

Intern at Vaidsys Technologies, Apr 2026 - Apr 2026 · 1 mo, Remote, Worked on designing and implementing a Pipelined MAC (Multiply-Accumulate) Unit using Verilog and Xilinx Vivado. Explored concepts such as Static Timing Analysis (STA), pipelining for timing optimization, and clock gating for low-power design. Simulated and verified different MAC architectures to compare performance, latency, and power behavior in digital VLSI systems.

Intern- Radar and ATC at Hindustan Aeronautics Limited, Jun 2025 - Jun 2025 · 1 mo, Bengaluru, Karnataka, India, Gained exposure to Radar and Air Traffic Control (ATC) systems, focusing on radar's working, target tracking, and communication protocols between aircraft and ground stations. Observed real time ATC operations including surveillance, handovers, and conflict resolution. Developed an understanding of radar-ATC integration, safety procedures, and the role of electronic systems in aviation control and monitoring.

Education

Bachelor of Engineering, Electrical, Electronics and Communications Engineering, Amrita Vishwa Vidyapeetham

Public links

github: https://github.com/aparna-chivukula

aparna-vedajnaa-chivukula-portfolio.netlify.app: https://aparna-vedajnaa-chivukula-portfolio.netlify.app/