Headline

Senior Lead Engineer at Qualcomm

About

A dedicated and experienced post silicon validation engineer with eight years of experience in validating and debugging multiple IP's such as PCIE, Ethernet, MIPI & SerDes. Proficient in analyzing and debugging complex problems using lab equipment such as oscilloscopes, logic analyzers, and BERT. Possesses a good understanding of system architecture, skilled at designing and executing validation plans, test cases, and scripts. Proven ability to collaborate effectively with cross-functional teams to resolve issues and improve product quality

Location

Bengaluru

AI stack

gemini

Microsoft Copilot

Work experience

Senior Lead Engineer at Qualcomm, Dec 2024 - Present · 1 yr 10 mos, Bengaluru, Karnataka, India

Mixed Signal Validation Engineer at Intel Corporation, Aug 2018 - Dec 2024 · 6 yrs 5 mos, Bengaluru Area, India, Experience in Electrical Validation of High Speed IOs like PCIE, Ethernet, MIPI & SerDes

Intern at Intel Corporation, Feb 2018 - May 2018 · 4 mos, Bengaluru Area, India

Student at Malviya National Institute of Technology, Jaipur, Jul 2016 - Jun 2018 · 2 yrs, Jaipur Area, India

Education

Master of Technology, Embedded Systems, Malviya National Institute of Technology, Jaipur

Bachelor of Engineering (B.E.), Electronics and Communications Engineering, Priyadarshini Institute of Engineering and Technology, CRPF Camp