---
title: "Chandan Cholin - Intern -Analog layout design in Davangere | Tal"
description: "Meet Chandan Cholin, Analog Layout Engineer | Cadence Virtuoso | Op-Amp & Standard Cell Layout | DRC/LVS | Altium Designer | Open to Work based in Davangere."
image: "https://tal.club/meet/chandan-cholin/share-image"
---

# Chandan Cholin on Tal

## Headline

Analog Layout Engineer \| Cadence Virtuoso \| Op\-Amp & Standard Cell Layout \| DRC/LVS \| Altium Designer \| Open to Work

## About

I am an Analog Layout Engineer with hands\-on experience in full custom IC layout and PCB layout, I have practical experience creating and validating both digital and analog layouts\. I successfully finished my training at Eklakshaya Innovation Labs, where I worked on a 2\-stage operational amplifier layout using Cadence Virtuoso and standard cell layouts \(Inverter, XOR, XNOR, and Inverter4x\)\. In accordance with industry\-standard layout practices, my work concentrated on matching strategies, floor planning, symmetry, routing, and reaching zero DRC and LVS errors\. I'm currently developing my Altium Designer skills to include PCB schematic entry, PCB layout design, and Gerber file generation in addition to IC layout\. My academic background and internship experience have also equipped me with strong research, technical documentation, and professional communication skills\. I am actively looking for entry\-level positions in PCB design and analog layout because I am passionate about lifelong learning and helping to create clean, dependable, and verified electronic designs\.

## Location

Davangere

## Work experience

Intern \-Analog layout design at ekLakshya Innovation Labs, Feb 2025 \- Jun 2025 · 5 mos, Bvb Hubli, \-Successfully completed training in Analog & Standard Cell Layout Design using Cadence Virtuoso\. \-Designed and verified layouts for Inverter, XOR, XNOR, and Inverter\-4x cells\. \-Implemented a 2\-stage Operational Amplifier layout, applying matching techniques, floor planning, symmetry, guard rings, and routing\. \-Achieved DRC\-clean and LVS\-matched layouts, ensuring manufacturability and layout quality\. \-Documented design flow and communicated effectively with mentors to meet project milestones\. \-Gained strong practical exposure to VLSI / Analog IC layout methodologies, improving attention to detail and problem\-solving skills\.

## Education

Bachelor of Engineering \- BE, Electrical, Electronics and Communications Engineering, SDM INSTITUTE OF TECHNOLOGY \(SDMIT\), UJIRE

Diploma, Electrical, Electronics and Communications Engineering, K H Kabbur institute of Engineering

[View the original profile](https://tal.club/meet/chandan-cholin)

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